sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

352

(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

338

(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

965

reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

966

RREG32_SOC15_IP(GC, reg) :

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

967

RREG32_SOC15_IP(MMHUB, reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5432

tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9077

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9083

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9130

mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9136

mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9244

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9258

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9290

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9304

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9335

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9434

tmp = RREG32_SOC15_IP(GC, target);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9444

tmp = RREG32_SOC15_IP(GC, target);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2219

tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6334

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6342

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6391

mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6399

mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6510

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6524

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6556

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6570

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6601

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6711

tmp = RREG32_SOC15_IP(GC, target);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6721

tmp = RREG32_SOC15_IP(GC, target);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1884

tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4716

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4724

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4767

mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4775

mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4886

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4900

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4932

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4946

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4977

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5986

mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5992

mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6047

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6083

cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

495

tmp = RREG32_SOC15_IP(MMHUB, reg);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

523

tmp = RREG32_SOC15_IP(MMHUB, reg);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

355

wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

357

wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

569

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

572

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

706

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

733

wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

767

doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

768

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

825

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

419

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

422

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

555

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

583

wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

613

doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

614

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

648

temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

654

temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

672

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

400

rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

403

ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

466

f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

498

rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

551

doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

552

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

576

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

583

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

589

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

599

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

609

ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

768

tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

771

tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

879

m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

404

rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

407

ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

459

mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

490

rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

547

doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

548

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

572

temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

579

temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

585

temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

594

temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

604

ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

718

tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

727

tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

733

ic_op_cntl = RREG32_SOC15_IP(GC,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

735

sdma_status = RREG32_SOC15_IP(GC,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

764

tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

899

m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 0,

sys/dev/pci/drm/amd/amdgpu/soc15.c

487

RREG32_SOC15_IP(GC, reg) : RREG32(reg);