RREG32_MC
tmp = RREG32_MC(R520_MC_STATUS);
tmp = RREG32_MC(R520_MC_CNTL0);
h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
tmp = RREG32_MC(RS480_GART_BASE);
tmp = RREG32_MC(RS480_GART_FEATURE_ID);
tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
tmp = RREG32_MC(0x5F);
tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
tmp = RREG32_MC(0x3B);
tmp = RREG32_MC(0x3C);
tmp = RREG32_MC(0x30);
tmp = RREG32_MC(0x31);
tmp = RREG32_MC(0x32);
tmp = RREG32_MC(0x33);
tmp = RREG32_MC(0x34);
tmp = RREG32_MC(0x35);
tmp = RREG32_MC(0x36);
tmp = RREG32_MC(0x37);
tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
tmp = RREG32_MC(R_000009_MC_CNTL1);
tmp = RREG32_MC(R_000009_MC_CNTL1);
if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
base = RREG32_MC(R_000004_MC_FB_LOCATION);
base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
tmp = RREG32_MC(MC_STATUS);
tmp = RREG32_MC(MC_MISC_LAT_TIMER);
tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;