Symbol: RREG32
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1507
uint32_t tmp_ = RREG32(reg); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1543
WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1546
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
142
data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
234
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
254
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
259
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
271
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
274
m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
276
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
328
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
59
(*dump)[i++][1] = RREG32(addr); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
141
(*dump)[i++][1] = RREG32(addr); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
175
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
195
temp = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
200
temp = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
212
RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
216
RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
218
RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_HI);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
246
while (!(RREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
260
reg = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
516
uint32_t status = RREG32(regSDMA_RLC0_CONTEXT_STATUS + reg_offset);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
517
uint32_t doorbell_off = RREG32(regSDMA_RLC0_DOORBELL_OFFSET + reg_offset);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
78
data = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1021
*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
116
while (!(RREG32(SOC15_REG_OFFSET(
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
392
data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
505
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
562
temp = RREG32(mmCP_HQD_IQ_TIMER);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
591
temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
638
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
643
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
655
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
658
m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
660
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
670
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
738
uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
750
RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
837
wave_cntl_prev = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
841
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
378
data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
492
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
562
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
567
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
579
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
582
m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
584
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
618
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
187
value = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
323
(*dump)[i++][1] = RREG32(addr); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
363
data = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
457
act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
462
if (low == RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_BASE)) &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
463
high == RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_BASE_HI)))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
480
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
519
temp = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
547
temp = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
552
temp = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
564
RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
567
m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
569
RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR_HI);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
115
(*dump)[i++][1] = RREG32(addr); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
107
while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
214
(*dump)[i++][1] = RREG32(addr); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
255
data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
329
act = RREG32(mmCP_HQD_ACTIVE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
334
if (low == RREG32(mmCP_HQD_PQ_BASE) &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
335
high == RREG32(mmCP_HQD_PQ_BASE_HI))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
351
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
397
temp = RREG32(mmCP_HQD_IQ_TIMER);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
426
temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
445
temp = RREG32(mmCP_HQD_ACTIVE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
471
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
476
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
488
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
491
m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
525
value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
559
uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
102
while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
177
value = RREG32(mmRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
238
(*dump)[i++][1] = RREG32(addr); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
278
data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
361
act = RREG32(mmCP_HQD_ACTIVE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
366
if (low == RREG32(mmCP_HQD_PQ_BASE) &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
367
high == RREG32(mmCP_HQD_PQ_BASE_HI))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
383
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
432
temp = RREG32(mmCP_HQD_IQ_TIMER);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
461
temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
480
temp = RREG32(mmCP_HQD_ACTIVE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
506
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
511
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
523
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
526
m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
536
value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
123
while (!(RREG32(SOC15_REG_OFFSET(
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
140
while (!(RREG32(SOC15_REG_OFFSET(
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
363
(*dump)[i++][1] = RREG32(addr); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
403
data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
516
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
588
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
593
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
605
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
608
m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
610
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
620
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
676
uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
691
RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
771
wave_cntl_prev = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
775
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK));
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1562
bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1581
bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1582
bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1600
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1613
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1624
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1803
r = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
406
mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
424
module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
707
dw_ptr[i] = RREG32(rom_data_offset);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c
47
return RREG32(offset);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
152
value = RREG32(*pos >> 2);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
281
value = RREG32(offset >> 2);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1531
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7591
(void)RREG32(address);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7592
r = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7607
(void)RREG32(address);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7609
(void)RREG32(data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7801
uint32_t tmp_ = RREG32(reg_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7810
tmp_ = RREG32(reg_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1819
vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
292
msg = RREG32(mmMP0_SMN_C2PMSG_33);
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
299
vram_size = RREG32(mmRCC_CONFIG_MEMSIZE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
617
(RREG32(mmIP_DISCOVERY_VERSION) == 4))
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
111
val = RREG32(rec->y_clk_reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
126
val = RREG32(rec->y_data_reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
140
val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
153
val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
53
temp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
59
temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
62
temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
66
temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
69
temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
73
temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
75
temp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
77
temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
79
temp = RREG32(rec->mask_data_reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
92
temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
94
temp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
96
temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
98
temp = RREG32(rec->mask_data_reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
169
RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
176
tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
253
tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
506
RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[0],
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
513
RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[j],
sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c
37
val = RREG32(reg_index);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
591
val = RREG32(reg_index);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
621
val = RREG32(reg_index);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5045
err_status_lo_data = RREG32(err_status_lo_offset);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5069
err_status_hi_data = RREG32(err_status_hi_offset);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c
82
return RREG32(umsch->rb_rptr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c
90
return RREG32(umsch->rb_wptr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1597
RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[0], i));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1605
RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[j], i));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
573
tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1186
return RREG32(offset);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
751
reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
761
reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
135
dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
213
dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
342
return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
712
rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
714
rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
731
wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
733
wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
885
context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1731
bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1776
bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1824
bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1825
bios_3_scratch = RREG32(mmBIOS_SCRATCH_3);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1826
bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
48
bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
62
bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
sys/dev/pci/drm/amd/amdgpu/cik.c
1037
dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1146
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/cik.c
1213
return RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/cik.c
1246
save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE);
sys/dev/pci/drm/amd/amdgpu/cik.c
1247
save->gmcon_misc = RREG32(mmGMCON_MISC);
sys/dev/pci/drm/amd/amdgpu/cik.c
1248
save->gmcon_misc3 = RREG32(mmGMCON_MISC3);
sys/dev/pci/drm/amd/amdgpu/cik.c
1359
if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
sys/dev/pci/drm/amd/amdgpu/cik.c
1448
return RREG32(mmCONFIG_MEMSIZE);
sys/dev/pci/drm/amd/amdgpu/cik.c
159
(void)RREG32(mmPCIE_INDEX);
sys/dev/pci/drm/amd/amdgpu/cik.c
160
r = RREG32(mmPCIE_DATA);
sys/dev/pci/drm/amd/amdgpu/cik.c
171
(void)RREG32(mmPCIE_INDEX);
sys/dev/pci/drm/amd/amdgpu/cik.c
173
(void)RREG32(mmPCIE_DATA);
sys/dev/pci/drm/amd/amdgpu/cik.c
184
r = RREG32(mmSMC_IND_DATA_0);
sys/dev/pci/drm/amd/amdgpu/cik.c
1854
return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
sys/dev/pci/drm/amd/amdgpu/cik.c
1862
RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik.c
1873
RREG32(mmHDP_DEBUG0);
sys/dev/pci/drm/amd/amdgpu/cik.c
206
r = RREG32(mmUVD_CTX_DATA);
sys/dev/pci/drm/amd/amdgpu/cik.c
228
r = RREG32(mmDIDT_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/cik.c
959
tmp = RREG32(mmCONFIG_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik.c
976
bus_cntl = RREG32(mmBUS_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik.c
978
d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/pci/drm/amd/amdgpu/cik.c
979
d2vga_control = RREG32(mmD2VGA_CONTROL);
sys/dev/pci/drm/amd/amdgpu/cik.c
980
vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
117
interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
204
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
351
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
367
tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
380
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
386
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
390
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
396
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
62
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
63
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
81
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
82
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1025
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1054
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1060
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1066
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1070
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1076
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1096
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1101
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1112
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1117
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
181
return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
314
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
371
f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
409
me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
882
orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
887
orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
900
orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
905
orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
910
orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
915
orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
117
interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
148
ih_cntl = RREG32(mmIH_CNTL);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
201
wptr = RREG32(mmIH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
215
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
347
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
363
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
375
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
382
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
386
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
392
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
62
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
63
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
81
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
82
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1125
wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1128
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1135
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1219
tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1485
tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1488
tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1492
tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1495
tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1499
tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1502
tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1550
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1594
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1600
tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1627
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1633
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1640
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1645
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1652
tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1659
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1664
tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1677
tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1681
tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1685
tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1717
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1724
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1728
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
180
r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1820
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2013
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
202
return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2034
tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2094
tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2113
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2118
tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2122
tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2126
tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2155
tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2161
tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2166
tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2171
tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2181
tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2280
cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2294
tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2310
tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
242
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
256
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
265
*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
266
*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2699
fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
288
if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2988
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2992
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2998
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3019
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3025
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3048
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3054
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3078
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3083
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
312
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3154
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3182
if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3228
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3243
tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3258
tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3268
uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3314
disp_int = RREG32(interrupt_status_offsets[hpd].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
349
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
355
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
359
tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
398
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
420
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
422
crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
430
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
449
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
457
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
491
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
495
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
628
tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
632
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
637
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
670
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1012
arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1021
tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1096
if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
143
r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1470
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1487
tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1493
tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1496
tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1500
tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1503
tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1507
tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1510
tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1551
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1572
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1600
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1604
tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1608
tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1612
tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1621
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1625
tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1630
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1644
tmp = RREG32(mmHDMI_GC + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1658
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
166
return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1665
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1669
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1673
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1680
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1695
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1699
tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1703
tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1864
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
220
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2253
cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
229
*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
230
*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
252
if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2666
fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
276
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2926
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2930
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2936
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
294
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2981
interrupt_mask = RREG32(mmINT_MASK + reg_block);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2986
interrupt_mask = RREG32(mmINT_MASK + reg_block);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3016
dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3021
dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3085
uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3129
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3157
if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3206
disp_int = RREG32(interrupt_status_offsets[hpd].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
321
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
332
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
367
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
388
if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
389
crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
397
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
415
RREG32(mmVGA_RENDER_CONTROL) & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
443
crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
447
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
523
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1078
wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1087
tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
131
r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
153
return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1566
val = RREG32(mmHDMI_CONTROL + offset);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1767
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
204
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
213
*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
214
*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2201
cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
236
if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
260
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2625
fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
278
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2898
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2902
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2908
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2953
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2958
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3004
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3009
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3032
dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3037
dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
305
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3101
uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3145
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
316
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3173
if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3222
disp_int = RREG32(interrupt_status_offsets[hpd].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
351
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
372
if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
373
crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
381
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
400
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
408
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
449
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
453
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
590
if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
623
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
107
*lo_val = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
109
*hi_val = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
153
lo_val_rb = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
155
hi_val_rb = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
59
ficadl_val = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
62
ficadh_val = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4056
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8224
reg_data = RREG32(reg_idx);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8232
reg_data = RREG32(reg_idx);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8241
reg_data = RREG32(reg_idx);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8308
pre_data = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9729
adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9748
RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9751
RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9777
RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2301
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5580
pre_data = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
585
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6807
r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6972
r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7098
adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i]));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7118
RREG32(SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7122
RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7148
RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c
44
rlc_status0 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_0));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c
45
rlc_status1 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_1));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1966
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3967
data = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
478
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5177
adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i]));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5194
RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5220
RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5280
r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1333
data = RREG32(mmCC_RB_BACKEND_DISABLE) |
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1334
RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1509
RREG32(mmCC_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1511
RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1513
RREG32(mmPA_SC_RASTER_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1538
data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1539
RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1556
data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1684
adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1747
sx_debug_1 = RREG32(mmSX_DEBUG_1);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1779
hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1807
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1924
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2133
return RREG32(mmCP_RB0_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2135
return RREG32(mmCP_RB1_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2137
return RREG32(mmCP_RB2_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2147
(void)RREG32(mmCP_RB0_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2156
(void)RREG32(mmCP_RB1_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2159
(void)RREG32(mmCP_RB2_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2239
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2253
tmp = RREG32(mmDB_DEPTH_INFO);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2257
if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2425
if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2431
if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2441
tmp = RREG32(mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2450
orig = data = RREG32(mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2492
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2551
orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2573
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2574
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2575
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2576
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2592
orig = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2598
orig = data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2604
orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2617
orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2622
data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2627
orig = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2671
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2760
(void)RREG32(mmDB_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2770
tmp = RREG32(mmRLC_MAX_PG_CU);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2781
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2795
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2812
tmp = RREG32(mmRLC_AUTO_PG_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2927
clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2928
((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2950
return RREG32(mmSQ_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2965
*(out++) = RREG32(mmSQ_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3173
if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3199
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3204
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3221
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3226
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3234
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3239
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3262
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3267
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3287
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3292
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1596
data = RREG32(mmCC_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1597
data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1800
RREG32(mmCC_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1802
RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1804
RREG32(mmPA_SC_RASTER_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1806
RREG32(mmPA_SC_RASTER_CONFIG_1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1962
tmp = RREG32(mmSPI_CONFIG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1970
tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1974
tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1978
tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2011
tmp = RREG32(mmSPI_ARB_PRIORITY);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2051
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2329
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2604
return RREG32(mmCP_RB0_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2612
(void)RREG32(mmCP_RB0_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2790
tmp = RREG32(mmCP_HPD_EOP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2804
if (RREG32(mmCP_HQD_ACTIVE) & 1) {
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2807
if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2842
RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2853
mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2862
mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2897
RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2916
mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2922
mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2923
mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2924
mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2925
mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2926
mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2927
mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2928
mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2929
mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2930
mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2931
mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2932
mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2933
mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2934
mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2935
mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2936
mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2937
mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2953
tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3014
tmp = RREG32(mmCP_CPF_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3065
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3257
tmp = RREG32(mmRLC_LB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3275
if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3289
if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3299
tmp = RREG32(mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3308
orig = data = RREG32(mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3317
if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3343
if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3349
if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3397
u32 tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3435
tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3480
data = RREG32(mmRLC_SPM_VMID);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3494
orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3520
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3521
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3522
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3523
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3540
orig = data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3547
orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3567
orig = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3582
orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3587
data = RREG32(mmRLC_MEM_SLP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3593
data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3599
orig = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3638
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3652
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3665
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3678
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3701
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3706
orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3711
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3716
orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3721
data = RREG32(mmDB_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3743
data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3744
data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3760
tmp = RREG32(mmRLC_MAX_PG_CU);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3771
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3785
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3818
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3826
data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3834
data = RREG32(mmRLC_PG_DELAY_2);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3839
data = RREG32(mmRLC_AUTO_PG_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3955
clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3956
((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4019
return RREG32(mmSQ_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4034
*(out++) = RREG32(mmSQ_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4213
adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4225
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4229
tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4484
if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4498
tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4514
tmp = RREG32(mmGRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4530
tmp = RREG32(mmGRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4535
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4554
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4558
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4564
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4568
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4572
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4578
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4593
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4598
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4644
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4649
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4667
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4672
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4692
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4697
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
5014
adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
5017
adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1492
tmp = RREG32(mmGB_EDC_MODE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1622
tmp = RREG32(mmCC_GC_EDC_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1629
RREG32(sec_ded_counter_registers[i]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1781
adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1793
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1797
tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3421
data = RREG32(mmCC_RB_BACKEND_DISABLE) |
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3422
RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3626
RREG32(mmCC_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3628
RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3630
RREG32(mmPA_SC_RASTER_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3632
RREG32(mmPA_SC_RASTER_CONFIG_1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3794
tmp = RREG32(mmSPI_ARB_PRIORITY);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3815
if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3837
if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3846
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4086
u32 tmp = RREG32(mmCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4200
tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4298
tmp = RREG32(mmRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4369
if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4372
if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4422
tmp = RREG32(mmCP_HQD_EOP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4429
tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4441
tmp = RREG32(mmCP_MQD_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4451
tmp = RREG32(mmCP_HQD_PQ_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4479
tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4496
mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4501
tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4506
tmp = RREG32(mmCP_HQD_IB_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4511
tmp = RREG32(mmCP_HQD_IQ_TIMER);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4515
tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4520
mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4521
mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4522
mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4523
mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4524
mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4525
mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4526
mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4527
mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4528
mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4529
mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4530
mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4531
mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4535
mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4802
if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4803
|| RREG32(mmGRBM_STATUS2) != 0x8)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4813
if (RREG32(mmGRBM_STATUS2) != 0x8)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4897
tmp = RREG32(mmGRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4914
tmp = RREG32(mmGRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4933
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5007
tmp = RREG32(mmGMCON_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5015
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5019
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5025
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5029
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5033
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5039
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5043
tmp = RREG32(mmGMCON_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5110
clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5111
((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5162
return RREG32(mmSQ_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5177
*(out++) = RREG32(mmSQ_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5312
RREG32(mmDB_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5408
data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5413
data = RREG32(mmRLC_CGCG_CGLS_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5422
data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5431
data = RREG32(mmRLC_MEM_SLP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5436
data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5451
data = RREG32(mmRLC_SERDES_WR_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5493
rlc_setting = RREG32(mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5504
data = RREG32(mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5512
if ((RREG32(mmRLC_GPM_STAT) &
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5521
if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5532
data = RREG32(mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5538
if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5553
data = RREG32(mmRLC_SPM_VMID);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5598
temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5620
temp = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5639
temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5648
data = RREG32(mmRLC_MEM_SLP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5655
data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5662
temp = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5686
temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5689
temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5713
temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5734
temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5741
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5742
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5743
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5744
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5982
return RREG32(mmCP_RB0_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5995
(void)RREG32(mmCP_RB0_WPTR);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6403
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6408
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6677
sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7013
adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7016
adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7037
data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7038
RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
856
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1213
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2847
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2931
default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2959
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2972
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2977
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2982
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2999
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3013
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3027
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3040
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3053
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3062
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3070
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3083
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7001
RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7064
RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7305
adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i]));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7324
RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7327
RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
886
reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
920
RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
990
reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1527
data = RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1634
data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1696
value = RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1726
reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1678
pre_data = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
428
tmp = RREG32(scratch_reg0_offset);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
440
tmp = RREG32(scratch_reg0_offset);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4661
RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i],
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4689
RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4695
RREG32(SOC15_REG_ENTRY_OFFSET_INST(
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
149
RREG32(hub->vm_l2_pro_fault_status);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
151
status = RREG32(hub->vm_l2_pro_fault_status);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
226
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
146
RREG32(hub->vm_l2_pro_fault_status);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
148
status = RREG32(hub->vm_l2_pro_fault_status);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
220
*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
139
RREG32(hub->vm_l2_pro_fault_status);
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
141
status = RREG32(hub->vm_l2_pro_fault_status);
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
213
*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1011
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1015
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1021
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1047
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1050
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1055
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1058
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1075
addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1076
status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
131
if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
168
running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
192
if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
197
if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
210
u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
246
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
251
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
277
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
285
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
318
adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
319
adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
399
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
430
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
675
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
692
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
730
orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
746
orig = data = RREG32(mmHDP_MEM_POWER_LS);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
75
blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
799
u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
805
u32 viewport = RREG32(mmVIEWPORT_SIZE);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
824
u32 tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
880
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
94
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
964
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
992
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1059
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1150
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
117
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1177
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1195
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1199
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1205
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1233
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1237
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1243
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1247
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1264
addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1265
status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1266
mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
199
running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
222
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
228
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
241
u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
283
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
288
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
307
tmp = RREG32(mmHDP_MISC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
311
tmp = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
334
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
340
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
374
adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
375
adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
389
adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
442
u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
450
RREG32(mmVM_INVALIDATE_RESPONSE);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
527
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
558
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
626
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
634
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
648
tmp = RREG32(mmVM_L2_CNTL3);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
660
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
690
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
702
tmp = RREG32(mmCHUB_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
746
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
752
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
833
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
850
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
888
orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
904
orig = data = RREG32(mmHDP_MEM_POWER_LS);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
968
u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
974
u32 viewport = RREG32(mmVIEWPORT_SIZE);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
99
blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
994
u32 tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1076
u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1082
u32 viewport = RREG32(mmVIEWPORT_SIZE);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1108
tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1110
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1174
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1273
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1290
tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1308
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1357
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1361
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1367
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1404
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1408
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1414
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1418
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1442
addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1443
status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1444
mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1509
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1513
data = RREG32(mmMC_HUB_MISC_SIP_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1517
data = RREG32(mmMC_HUB_MISC_VM_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1521
data = RREG32(mmMC_XPB_CLK_GAT);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1525
data = RREG32(mmATC_MISC_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1529
data = RREG32(mmMC_CITF_MISC_WR_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1533
data = RREG32(mmMC_CITF_MISC_RD_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1537
data = RREG32(mmMC_CITF_MISC_VM_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1541
data = RREG32(mmVM_L2_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1545
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1549
data = RREG32(mmMC_HUB_MISC_SIP_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1553
data = RREG32(mmMC_HUB_MISC_VM_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1557
data = RREG32(mmMC_XPB_CLK_GAT);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1561
data = RREG32(mmATC_MISC_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1565
data = RREG32(mmMC_CITF_MISC_WR_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1569
data = RREG32(mmMC_CITF_MISC_RD_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1573
data = RREG32(mmMC_CITF_MISC_VM_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1577
data = RREG32(mmVM_L2_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1589
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1593
data = RREG32(mmMC_HUB_MISC_SIP_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1597
data = RREG32(mmMC_HUB_MISC_VM_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1601
data = RREG32(mmMC_XPB_CLK_GAT);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1605
data = RREG32(mmATC_MISC_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1609
data = RREG32(mmMC_CITF_MISC_WR_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1613
data = RREG32(mmMC_CITF_MISC_RD_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1617
data = RREG32(mmMC_CITF_MISC_VM_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1621
data = RREG32(mmVM_L2_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1625
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1629
data = RREG32(mmMC_HUB_MISC_SIP_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1633
data = RREG32(mmMC_HUB_MISC_VM_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1637
data = RREG32(mmMC_XPB_CLK_GAT);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1641
data = RREG32(mmATC_MISC_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1645
data = RREG32(mmMC_CITF_MISC_WR_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1649
data = RREG32(mmMC_CITF_MISC_RD_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1653
data = RREG32(mmMC_CITF_MISC_VM_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1657
data = RREG32(mmVM_L2_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1699
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
181
blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
199
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
247
if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
309
running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
332
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
338
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
378
data = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
402
data = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
417
base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
458
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
463
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
493
tmp = RREG32(mmHDP_MISC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
497
tmp = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
520
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
526
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
560
tmp = RREG32(mmCONFIG_MEMSIZE);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
580
adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
633
u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
641
RREG32(mmVM_INVALIDATE_RESPONSE);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
742
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
775
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
843
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
851
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
860
tmp = RREG32(mmVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
866
tmp = RREG32(mmVM_L2_CNTL3);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
872
tmp = RREG32(mmVM_L2_CNTL4);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
893
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
923
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
980
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
986
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1861
vram_info = RREG32(regBIF_BIOS_SCRATCH_4);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
431
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
437
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
445
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
451
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
660
RREG32(hub->vm_l2_pro_fault_status);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
662
status = RREG32(hub->vm_l2_pro_fault_status);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
816
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
102
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
132
data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
92
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
117
interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
148
ih_cntl = RREG32(mmIH_CNTL);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
201
wptr = RREG32(mmIH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
214
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
341
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
357
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
369
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
376
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
380
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
386
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
62
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
63
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
81
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
82
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
136
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
277
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
136
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
249
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
136
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
249
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
249
data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
261
data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
467
if (!(RREG32(reg) & value))
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
492
if (!(RREG32(reg) & value))
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
807
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
825
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1281
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1321
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1340
reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
1642
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
1659
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
1684
RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i]));
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
161
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
275
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
117
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
140
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
94
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
73
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
89
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
168
doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
193
doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nv.c
288
r = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/nv.c
366
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/nv.c
383
return RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
895
pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1000
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1011
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1016
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
205
u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
344
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
347
ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
384
f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
428
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
461
ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
917
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
933
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
947
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
951
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
958
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
965
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
969
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
975
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
995
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1206
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1222
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1236
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1303
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1307
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1313
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1333
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1338
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1349
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1354
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1432
temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1446
temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1471
temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1479
temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1526
data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1531
data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
369
wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
520
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
523
ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
579
f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
621
f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
668
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
695
doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
713
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
731
ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1258
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1265
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1277
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
128
RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1283
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1289
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2343
data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2348
data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2388
RREG32(sdma_v4_0_get_reg_offset(adev, i,
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c
205
reg_value = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c
212
reg_value = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
103
RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1653
uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2040
data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2045
data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2085
RREG32(sdma_v4_4_2_get_reg_offset(adev, i,
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1502
u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1518
sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1519
sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1574
freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1579
freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1587
stat1_reg = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1595
f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1599
cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1616
freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1685
sdma_cntl = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1770
def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1783
def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1807
def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1814
def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1862
data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1867
data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1908
RREG32(sdma_v5_0_get_reg_offset(adev, i,
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
629
f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
672
f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
793
temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
801
temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
807
temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
816
temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
975
m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
986
m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1415
u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1431
sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1432
sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1433
sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1434
sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1482
freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1487
freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1496
stat1_reg = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1504
f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1508
cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1526
freeze = RREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1591
sdma_cntl = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1736
def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1747
def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1774
def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1781
def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1834
data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1910
RREG32(sdma_v5_2_get_reg_offset(adev, i,
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
195
wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
197
wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
488
f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
519
f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
640
temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
663
temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
875
m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
886
m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1495
u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1511
sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1512
sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1601
sdma_cntl = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1721
RREG32(sdma_v6_0_get_reg_offset(adev, i,
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
436
f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1451
u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1467
sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1468
sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1535
sdma_cntl = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1654
RREG32(sdma_v7_0_get_reg_offset(adev, i,
sys/dev/pci/drm/amd/amdgpu/si.c
1039
(void)RREG32(AMDGPU_PCIE_INDEX);
sys/dev/pci/drm/amd/amdgpu/si.c
1040
r = RREG32(AMDGPU_PCIE_DATA);
sys/dev/pci/drm/amd/amdgpu/si.c
1051
(void)RREG32(AMDGPU_PCIE_INDEX);
sys/dev/pci/drm/amd/amdgpu/si.c
1053
(void)RREG32(AMDGPU_PCIE_DATA);
sys/dev/pci/drm/amd/amdgpu/si.c
1064
(void)RREG32(PCIE_PORT_INDEX);
sys/dev/pci/drm/amd/amdgpu/si.c
1065
r = RREG32(PCIE_PORT_DATA);
sys/dev/pci/drm/amd/amdgpu/si.c
1076
(void)RREG32(PCIE_PORT_INDEX);
sys/dev/pci/drm/amd/amdgpu/si.c
1078
(void)RREG32(PCIE_PORT_DATA);
sys/dev/pci/drm/amd/amdgpu/si.c
1089
r = RREG32(mmSMC_IND_DATA_0);
sys/dev/pci/drm/amd/amdgpu/si.c
1111
r = RREG32(mmUVD_CTX_DATA);
sys/dev/pci/drm/amd/amdgpu/si.c
1200
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/si.c
1249
return RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/si.c
1281
bus_cntl = RREG32(mmBUS_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1283
d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/pci/drm/amd/amdgpu/si.c
1284
d2vga_control = RREG32(mmD2VGA_CONTROL);
sys/dev/pci/drm/amd/amdgpu/si.c
1285
vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/si.c
1287
rom_cntl = RREG32(R600_ROM_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1339
dw_ptr[i] = RREG32(mmROM_DATA);
sys/dev/pci/drm/amd/amdgpu/si.c
1348
tmp = RREG32(mmCG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1352
tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/amd/amdgpu/si.c
1357
if (RREG32(mmCG_SPLL_STATUS) & CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK)
sys/dev/pci/drm/amd/amdgpu/si.c
1362
tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/amd/amdgpu/si.c
1367
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/pci/drm/amd/amdgpu/si.c
1376
tmp = RREG32(mmSPLL_CNTL_MODE);
sys/dev/pci/drm/amd/amdgpu/si.c
1380
tmp = RREG32(mmCG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1384
tmp = RREG32(mmCG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1388
tmp = RREG32(mmSPLL_CNTL_MODE);
sys/dev/pci/drm/amd/amdgpu/si.c
1413
if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
sys/dev/pci/drm/amd/amdgpu/si.c
1465
return RREG32(mmCONFIG_MEMSIZE);
sys/dev/pci/drm/amd/amdgpu/si.c
1472
temp = RREG32(mmCONFIG_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1487
tmp = RREG32(mmCG_CLKPIN_CNTL_2);
sys/dev/pci/drm/amd/amdgpu/si.c
1491
tmp = RREG32(mmCG_CLKPIN_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1502
RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1513
RREG32(mmHDP_DEBUG0);
sys/dev/pci/drm/amd/amdgpu/si.c
1670
if ((RREG32(cg_upll_func_cntl) & mask) == mask)
sys/dev/pci/drm/amd/amdgpu/si.c
2036
return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
sys/dev/pci/drm/amd/amdgpu/si.c
2391
r = RREG32(EVERGREEN_PIF_PHY0_DATA);
sys/dev/pci/drm/amd/amdgpu/si.c
2413
r = RREG32(EVERGREEN_PIF_PHY1_DATA);
sys/dev/pci/drm/amd/amdgpu/si.c
2571
orig = data = RREG32(mmTHM_CLK_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
2577
orig = data = RREG32(mmMISC_CLK_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
2583
orig = data = RREG32(mmCG_CLKPIN_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
2588
orig = data = RREG32(mmCG_CLKPIN_CNTL_2);
sys/dev/pci/drm/amd/amdgpu/si.c
2593
orig = data = RREG32(mmMPLL_BYPASSCLK_SEL);
sys/dev/pci/drm/amd/amdgpu/si.c
2599
orig = data = RREG32(mmSPLL_CNTL_MODE);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
136
rb_cntl = RREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
183
dma_cntl = RREG32(mmDMA_CNTL + sdma_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
564
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
602
sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
607
sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
618
sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
623
sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
664
orig = data = RREG32(mmDMA_POWER_CNTL + offset);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
67
return (RREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
676
orig = data = RREG32(mmDMA_POWER_CNTL + offset);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
681
orig = data = RREG32(mmDMA_CLK_CTRL + offset);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
120
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
217
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
243
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
249
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
253
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
259
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
38
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
39
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
50
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
51
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
72
interrupt_cntl = RREG32(INTERRUPT_CNTL);
sys/dev/pci/drm/amd/amdgpu/soc15.c
1377
def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
sys/dev/pci/drm/amd/amdgpu/soc15.c
1406
def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
sys/dev/pci/drm/amd/amdgpu/soc15.c
1488
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
sys/dev/pci/drm/amd/amdgpu/soc15.c
1493
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
sys/dev/pci/drm/amd/amdgpu/soc15.c
250
r = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/soc15.c
278
r = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/soc15.c
413
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/soc15.c
432
return RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/soc15.c
487
RREG32_SOC15_IP(GC, reg) : RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
125
u32 tmp = RREG32(r1); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
48
RREG32(reg))
sys/dev/pci/drm/amd/amdgpu/soc21.c
203
r = RREG32(data);
sys/dev/pci/drm/amd/amdgpu/soc21.c
287
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/soc21.c
304
return RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/soc24.c
146
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/soc24.c
164
return RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
113
interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
145
ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
203
wptr = RREG32(mmIH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
218
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
359
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
375
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
387
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
432
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
436
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
442
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
62
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
79
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
155
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
213
tmp = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
291
if (RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__DONE_MASK)
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
298
if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__PASS_MASK))
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
303
if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__BUSY_MASK))
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
358
tmp = RREG32(mmUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
385
status = RREG32(mmUVD_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
426
ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
456
status = RREG32(mmUVD_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
467
status = RREG32(mmUVD_LMI_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
48
return RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
481
status = RREG32(mmUVD_LMI_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
605
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
614
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
62
return RREG32(mmUVD_RBC_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
722
if (RREG32(mmUVD_STATUS) != 0)
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
786
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
795
if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
215
if (RREG32(mmUVD_STATUS) != 0)
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
319
tmp = RREG32(mmUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
348
status = RREG32(mmUVD_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
389
ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
419
status = RREG32(mmUVD_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
430
status = RREG32(mmUVD_LMI_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
444
status = RREG32(mmUVD_LMI_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
522
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
619
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
62
return RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
628
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
642
tmp = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
666
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
675
if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
76
return RREG32(mmUVD_RBC_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
213
if (RREG32(mmUVD_STATUS) != 0)
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
391
status = RREG32(mmUVD_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
445
ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
536
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
587
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
596
if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
60
return RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
637
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
638
data3 = RREG32(mmUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
683
data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
684
data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
731
data = RREG32(mmUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
732
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
74
return RREG32(mmUVD_RBC_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
777
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
786
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
854
data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1002
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
111
return RREG32(mmUVD_RBC_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1152
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1172
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1176
(RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1211
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1215
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1221
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
126
return RREG32(mmUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
128
return RREG32(mmUVD_RB_WPTR2);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1287
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1288
data3 = RREG32(mmUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1342
data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1343
data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1391
data = RREG32(mmUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1392
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1439
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1448
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1521
data = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
539
if (RREG32(mmUVD_STATUS) != 0)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
646
data = RREG32(mmUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
647
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
808
status = RREG32(mmUVD_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
81
return RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
862
ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
96
return RREG32(mmUVD_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
98
return RREG32(mmUVD_RB_RPTR2);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
105
uint32_t status = RREG32(mmVCE_LMI_STATUS);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
122
uint32_t status = RREG32(mmVCE_STATUS);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
151
tmp = RREG32(mmVCE_CLOCK_GATING_A);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
157
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
162
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
208
return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
300
status = RREG32(mmVCE_LMI_STATUS);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
321
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
325
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
329
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
335
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
340
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
345
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
358
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
371
orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
377
orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
60
return RREG32(mmVCE_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
62
return RREG32(mmVCE_RB_RPTR2);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
77
return RREG32(mmVCE_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
79
return RREG32(mmVCE_RB_WPTR2);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
122
v = RREG32(mmVCE_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
124
v = RREG32(mmVCE_RB_WPTR2);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
126
v = RREG32(mmVCE_RB_WPTR3);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
182
data = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
187
data = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
192
data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
197
data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
201
data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
208
data = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
213
data = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
217
data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
221
data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
225
data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
241
uint32_t status = RREG32(mmVCE_STATUS);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
608
return !(RREG32(mmSRBM_STATUS2) & mask);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
649
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
654
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
682
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
686
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
692
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
783
uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
789
data = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
851
data = RREG32(mmVCE_CLOCK_GATING_A);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
90
v = RREG32(mmVCE_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
92
v = RREG32(mmVCE_RB_RPTR2);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
94
v = RREG32(mmVCE_RB_RPTR3);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
132
RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
168
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
187
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
191
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
67
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
69
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
71
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
89
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
91
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
93
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2030
RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1845
tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
105
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
220
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
113
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
256
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vi.c
1230
orig = data = RREG32(mmBIF_CLK_CTRL);
sys/dev/pci/drm/amd/amdgpu/vi.c
1287
tmp = RREG32(mmBIF_DOORBELL_APER_EN);
sys/dev/pci/drm/amd/amdgpu/vi.c
1306
return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
sys/dev/pci/drm/amd/amdgpu/vi.c
1314
RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
sys/dev/pci/drm/amd/amdgpu/vi.c
1325
RREG32(mmHDP_DEBUG0);
sys/dev/pci/drm/amd/amdgpu/vi.c
1768
temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/pci/drm/amd/amdgpu/vi.c
1784
temp = data = RREG32(mmHDP_MEM_POWER_LS);
sys/dev/pci/drm/amd/amdgpu/vi.c
1800
temp = data = RREG32(0x157a);
sys/dev/pci/drm/amd/amdgpu/vi.c
2010
data = RREG32(mmHDP_MEM_POWER_LS);
sys/dev/pci/drm/amd/amdgpu/vi.c
2015
data = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/pci/drm/amd/amdgpu/vi.c
355
r = RREG32(mmMP0PUB_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/vi.c
377
r = RREG32(mmUVD_CTX_DATA);
sys/dev/pci/drm/amd/amdgpu/vi.c
399
r = RREG32(mmDIDT_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/vi.c
421
r = RREG32(mmGC_CAC_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/vi.c
598
bus_cntl = RREG32(mmBUS_CNTL);
sys/dev/pci/drm/amd/amdgpu/vi.c
600
d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/pci/drm/amd/amdgpu/vi.c
601
d2vga_control = RREG32(mmD2VGA_CONTROL);
sys/dev/pci/drm/amd/amdgpu/vi.c
602
vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/vi.c
659
dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
sys/dev/pci/drm/amd/amdgpu/vi.c
768
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/vi.c
835
return RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/vi.c
884
if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
sys/dev/pci/drm/amd/amdgpu/vi.c
977
return RREG32(mmCONFIG_MEMSIZE);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
109
vpe_colla_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
114
vpe_colla_cfg = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
136
ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
138
ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
162
f32_cntl = RREG32(f32_offset);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
218
rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
250
doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
254
doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
264
ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
284
queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ_6_1_1));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
286
queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
318
vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL_6_1_1));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
320
vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
79
f32_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL));
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
126
u32 v = RREG32(mmDOUT_SCRATCH3);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
422
data = RREG32(config_regs->offset);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
101
*value = RREG32(mmSMC_IND_DATA_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
142
original_data = RREG32(mmSMC_IND_DATA_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
196
original_data = RREG32(mmSMC_IND_DATA_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
40
if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
44
tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2212
cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2779
reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2864
data = RREG32(config_regs->offset);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3107
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3108
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3109
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3112
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3113
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3114
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3117
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3118
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3119
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3122
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3123
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3124
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3155
mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3412
return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3729
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3735
width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3737
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4091
si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4092
si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4093
si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4094
si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4095
si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4096
si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4097
si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4098
si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4099
si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4100
si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4101
si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4102
si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4103
si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4104
si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4105
si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4141
if (RREG32(SMC_RESP_0) == 1)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4211
tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4224
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4316
u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4794
u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4801
dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4824
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4825
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4826
burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5547
(RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5563
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5564
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5566
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5574
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5896
temp_reg = RREG32(MC_PMG_CMD_EMRS);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5907
temp_reg = RREG32(MC_PMG_CMD_MRS);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5931
temp_reg = RREG32(MC_PMG_CMD_MRS1);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6068
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6069
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6070
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6071
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6072
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6073
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6074
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6075
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6076
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6077
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6078
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6079
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6080
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6081
WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6467
u32 thermal_int = RREG32(mmCG_THERMAL_INT);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6518
tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6520
tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6525
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6529
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6550
duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6586
tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6645
duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6646
duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6676
duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6685
tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6727
tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6746
tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6775
tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6791
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6795
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6815
tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6820
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7585
(RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7938
temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
8070
(RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
130
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
131
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
132
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
133
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
197
tmp = RREG32(mmSMC_RESP_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
203
tmp = RREG32(mmSMC_RESP_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
207
__func__, msg, RREG32(mmSMC_SCRATCH0));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
282
*value = RREG32(mmSMC_IND_DATA_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
92
original_data = RREG32(mmSMC_IND_DATA_0);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
34
data = RREG32(reg);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
56
data = RREG32(reg);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
44
reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
57
reg = RREG32(mmBACO_CNTL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c
40
data = RREG32(0x12075);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
47
if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
117
reg = RREG32(smu->resp_reg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
139
msg_idx = RREG32(smu->msg_reg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
140
prm = RREG32(smu->param_reg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
285
resp = RREG32(smu->resp_reg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
70
*arg = RREG32(smu->param_reg);
sys/dev/pci/drm/radeon/atombios_crtc.c
1702
disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
sys/dev/pci/drm/radeon/atombios_crtc.c
1707
disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
sys/dev/pci/drm/radeon/atombios_crtc.c
1710
WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
sys/dev/pci/drm/radeon/atombios_crtc.c
1711
WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
sys/dev/pci/drm/radeon/atombios_crtc.c
238
vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
sys/dev/pci/drm/radeon/atombios_crtc.c
402
ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
sys/dev/pci/drm/radeon/atombios_crtc.c
407
ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
sys/dev/pci/drm/radeon/atombios_crtc.c
418
ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
sys/dev/pci/drm/radeon/atombios_crtc.c
423
ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
sys/dev/pci/drm/radeon/atombios_encoders.c
1544
temp = RREG32(reg);
sys/dev/pci/drm/radeon/atombios_encoders.c
1619
u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
sys/dev/pci/drm/radeon/atombios_encoders.c
2006
uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
sys/dev/pci/drm/radeon/atombios_encoders.c
2335
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
sys/dev/pci/drm/radeon/atombios_encoders.c
2337
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
sys/dev/pci/drm/radeon/atombios_encoders.c
2384
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
sys/dev/pci/drm/radeon/atombios_encoders.c
54
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
sys/dev/pci/drm/radeon/atombios_encoders.c
56
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
sys/dev/pci/drm/radeon/atombios_encoders.c
71
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
sys/dev/pci/drm/radeon/atombios_encoders.c
73
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
sys/dev/pci/drm/radeon/btc_dpm.c
1314
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/pci/drm/radeon/btc_dpm.c
1333
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/pci/drm/radeon/btc_dpm.c
1417
tmp = RREG32(sequence[i]);
sys/dev/pci/drm/radeon/btc_dpm.c
1714
if (((RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK) >> LB_SYNC_RESET_SEL_SHIFT) != 1)
sys/dev/pci/drm/radeon/btc_dpm.c
1729
arb_registers->mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/radeon/btc_dpm.c
1730
arb_registers->mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/radeon/btc_dpm.c
1731
arb_registers->mc_arb_rfsh_rate = RREG32(MC_ARB_RFSH_RATE);
sys/dev/pci/drm/radeon/btc_dpm.c
1732
arb_registers->mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
sys/dev/pci/drm/radeon/btc_dpm.c
1896
tmp = RREG32(MC_PMG_CMD_EMRS);
sys/dev/pci/drm/radeon/btc_dpm.c
1909
tmp = RREG32(MC_PMG_CMD_MRS);
sys/dev/pci/drm/radeon/btc_dpm.c
1925
tmp = RREG32(MC_PMG_CMD_MRS1);
sys/dev/pci/drm/radeon/btc_dpm.c
2000
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/radeon/btc_dpm.c
2001
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/radeon/btc_dpm.c
2002
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/radeon/btc_dpm.c
2003
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/radeon/btc_dpm.c
2004
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/radeon/btc_dpm.c
2005
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/radeon/btc_dpm.c
2006
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/radeon/btc_dpm.c
2007
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/radeon/btc_dpm.c
2008
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/radeon/btc_dpm.c
2009
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/radeon/btc_dpm.c
2010
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/radeon/btc_dpm.c
2043
tmp = RREG32(MC_PMG_AUTO_CFG);
sys/dev/pci/drm/radeon/btc_dpm.c
2713
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/btc_dpm.c
2738
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/btc_dpm.c
2761
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/ci_dpm.c
1626
tmp = RREG32(SMC_RESP_0);
sys/dev/pci/drm/radeon/ci_dpm.c
1631
tmp = RREG32(SMC_RESP_0);
sys/dev/pci/drm/radeon/ci_dpm.c
1651
*parameter = RREG32(SMC_MSG_ARG_0);
sys/dev/pci/drm/radeon/ci_dpm.c
1844
pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
1845
pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
1846
pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
1847
pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
1848
pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
1849
pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
sys/dev/pci/drm/radeon/ci_dpm.c
1850
pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/ci_dpm.c
1851
pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/pci/drm/radeon/ci_dpm.c
1852
pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/pci/drm/radeon/ci_dpm.c
1903
if (RREG32(SMC_RESP_0) == 1)
sys/dev/pci/drm/radeon/ci_dpm.c
2459
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/ci_dpm.c
2489
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/radeon/ci_dpm.c
2490
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/radeon/ci_dpm.c
2491
burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
2888
(RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
sys/dev/pci/drm/radeon/ci_dpm.c
2909
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/pci/drm/radeon/ci_dpm.c
2910
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ci_dpm.c
2912
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ci_dpm.c
2918
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ci_dpm.c
4298
temp_reg = RREG32(MC_PMG_CMD_EMRS);
sys/dev/pci/drm/radeon/ci_dpm.c
4309
temp_reg = RREG32(MC_PMG_CMD_MRS);
sys/dev/pci/drm/radeon/ci_dpm.c
4335
temp_reg = RREG32(MC_PMG_CMD_MRS1);
sys/dev/pci/drm/radeon/ci_dpm.c
4491
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/ci_dpm.c
4565
tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
sys/dev/pci/drm/radeon/ci_dpm.c
4586
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/radeon/ci_dpm.c
4587
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/radeon/ci_dpm.c
4588
WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
sys/dev/pci/drm/radeon/ci_dpm.c
4589
WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
sys/dev/pci/drm/radeon/ci_dpm.c
4590
WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
sys/dev/pci/drm/radeon/ci_dpm.c
4591
WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
sys/dev/pci/drm/radeon/ci_dpm.c
4592
WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
sys/dev/pci/drm/radeon/ci_dpm.c
4593
WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
sys/dev/pci/drm/radeon/ci_dpm.c
4594
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/radeon/ci_dpm.c
4595
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/radeon/ci_dpm.c
4596
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/radeon/ci_dpm.c
4597
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/radeon/ci_dpm.c
4598
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/radeon/ci_dpm.c
4599
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/radeon/ci_dpm.c
4600
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/radeon/ci_dpm.c
4601
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/radeon/ci_dpm.c
4602
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/radeon/ci_dpm.c
4603
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/pci/drm/radeon/ci_dpm.c
4604
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/pci/drm/radeon/ci_dpm.c
4605
WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
sys/dev/pci/drm/radeon/ci_dpm.c
5042
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/ci_dpm.c
560
data = RREG32(config_regs->offset << 2);
sys/dev/pci/drm/radeon/ci_smc.c
255
*value = RREG32(SMC_IND_DATA_0);
sys/dev/pci/drm/radeon/ci_smc.c
88
original_data = RREG32(SMC_IND_DATA_0);
sys/dev/pci/drm/radeon/cik.c
169
*val = RREG32(reg);
sys/dev/pci/drm/radeon/cik.c
186
r = RREG32(CIK_DIDT_IND_DATA);
sys/dev/pci/drm/radeon/cik.c
1902
running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
sys/dev/pci/drm/radeon/cik.c
1920
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/cik.c
1943
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
sys/dev/pci/drm/radeon/cik.c
1948
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
sys/dev/pci/drm/radeon/cik.c
244
(void)RREG32(PCIE_INDEX);
sys/dev/pci/drm/radeon/cik.c
245
r = RREG32(PCIE_DATA);
sys/dev/pci/drm/radeon/cik.c
256
(void)RREG32(PCIE_INDEX);
sys/dev/pci/drm/radeon/cik.c
258
(void)RREG32(PCIE_DATA);
sys/dev/pci/drm/radeon/cik.c
3077
data = RREG32(CC_RB_BACKEND_DISABLE);
sys/dev/pci/drm/radeon/cik.c
3082
data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
sys/dev/pci/drm/radeon/cik.c
3170
u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
sys/dev/pci/drm/radeon/cik.c
3264
RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/cik.c
3265
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/cik.c
3354
tmp = RREG32(SPI_CONFIG_CNTL);
sys/dev/pci/drm/radeon/cik.c
3362
tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
sys/dev/pci/drm/radeon/cik.c
3366
tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
sys/dev/pci/drm/radeon/cik.c
3370
tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
sys/dev/pci/drm/radeon/cik.c
3396
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/pci/drm/radeon/cik.c
3400
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/cik.c
3470
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/cik.c
3815
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/cik.c
4121
rptr = RREG32(CP_RB0_RPTR);
sys/dev/pci/drm/radeon/cik.c
4129
return RREG32(CP_RB0_WPTR);
sys/dev/pci/drm/radeon/cik.c
4136
(void)RREG32(CP_RB0_WPTR);
sys/dev/pci/drm/radeon/cik.c
4149
rptr = RREG32(CP_HQD_PQ_RPTR);
sys/dev/pci/drm/radeon/cik.c
4168
wptr = RREG32(CP_HQD_PQ_WPTR);
sys/dev/pci/drm/radeon/cik.c
4191
tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
sys/dev/pci/drm/radeon/cik.c
4195
if (RREG32(CP_HQD_ACTIVE) & 1) {
sys/dev/pci/drm/radeon/cik.c
4198
if (!(RREG32(CP_HQD_ACTIVE) & 1))
sys/dev/pci/drm/radeon/cik.c
4525
tmp = RREG32(CP_CPF_DEBUG);
sys/dev/pci/drm/radeon/cik.c
4547
tmp = RREG32(CP_HPD_EOP_CONTROL);
sys/dev/pci/drm/radeon/cik.c
4610
tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
sys/dev/pci/drm/radeon/cik.c
4616
RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/pci/drm/radeon/cik.c
4628
if (RREG32(CP_HQD_ACTIVE) & 1) {
sys/dev/pci/drm/radeon/cik.c
4631
if (!(RREG32(CP_HQD_ACTIVE) & 1))
sys/dev/pci/drm/radeon/cik.c
4646
mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
sys/dev/pci/drm/radeon/cik.c
4658
mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
sys/dev/pci/drm/radeon/cik.c
4702
RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/pci/drm/radeon/cik.c
4720
mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
sys/dev/pci/drm/radeon/cik.c
4796
RREG32(GRBM_STATUS));
sys/dev/pci/drm/radeon/cik.c
4798
RREG32(GRBM_STATUS2));
sys/dev/pci/drm/radeon/cik.c
4800
RREG32(GRBM_STATUS_SE0));
sys/dev/pci/drm/radeon/cik.c
4802
RREG32(GRBM_STATUS_SE1));
sys/dev/pci/drm/radeon/cik.c
4804
RREG32(GRBM_STATUS_SE2));
sys/dev/pci/drm/radeon/cik.c
4806
RREG32(GRBM_STATUS_SE3));
sys/dev/pci/drm/radeon/cik.c
4808
RREG32(SRBM_STATUS));
sys/dev/pci/drm/radeon/cik.c
4810
RREG32(SRBM_STATUS2));
sys/dev/pci/drm/radeon/cik.c
4812
RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
sys/dev/pci/drm/radeon/cik.c
4814
RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
sys/dev/pci/drm/radeon/cik.c
4815
dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT));
sys/dev/pci/drm/radeon/cik.c
4817
RREG32(CP_STALLED_STAT1));
sys/dev/pci/drm/radeon/cik.c
4819
RREG32(CP_STALLED_STAT2));
sys/dev/pci/drm/radeon/cik.c
4821
RREG32(CP_STALLED_STAT3));
sys/dev/pci/drm/radeon/cik.c
4823
RREG32(CP_CPF_BUSY_STAT));
sys/dev/pci/drm/radeon/cik.c
4825
RREG32(CP_CPF_STALLED_STAT1));
sys/dev/pci/drm/radeon/cik.c
4826
dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));
sys/dev/pci/drm/radeon/cik.c
4827
dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));
sys/dev/pci/drm/radeon/cik.c
4829
RREG32(CP_CPC_STALLED_STAT1));
sys/dev/pci/drm/radeon/cik.c
4830
dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));
sys/dev/pci/drm/radeon/cik.c
4848
tmp = RREG32(GRBM_STATUS);
sys/dev/pci/drm/radeon/cik.c
4861
tmp = RREG32(GRBM_STATUS2);
sys/dev/pci/drm/radeon/cik.c
4866
tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
4871
tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
4876
tmp = RREG32(SRBM_STATUS2);
sys/dev/pci/drm/radeon/cik.c
4884
tmp = RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/cik.c
4935
RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
sys/dev/pci/drm/radeon/cik.c
4937
RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
sys/dev/pci/drm/radeon/cik.c
4954
tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
4960
tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
5009
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5013
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5019
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5023
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5027
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5033
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5054
save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
sys/dev/pci/drm/radeon/cik.c
5055
save->gmcon_misc = RREG32(GMCON_MISC);
sys/dev/pci/drm/radeon/cik.c
5056
save->gmcon_misc3 = RREG32(GMCON_MISC3);
sys/dev/pci/drm/radeon/cik.c
5157
tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
5161
tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
5189
if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
sys/dev/pci/drm/radeon/cik.c
5335
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/cik.c
5341
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/cik.c
5377
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/pci/drm/radeon/cik.c
5378
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/pci/drm/radeon/cik.c
5496
u32 tmp = RREG32(CHUB_CONTROL);
sys/dev/pci/drm/radeon/cik.c
5546
rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
sys/dev/pci/drm/radeon/cik.c
5621
u64 tmp = RREG32(MC_VM_FB_OFFSET);
sys/dev/pci/drm/radeon/cik.c
5760
u32 tmp = RREG32(CP_INT_CNTL_RING0);
sys/dev/pci/drm/radeon/cik.c
5773
tmp = RREG32(RLC_LB_CNTL);
sys/dev/pci/drm/radeon/cik.c
5790
if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
sys/dev/pci/drm/radeon/cik.c
5800
if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
sys/dev/pci/drm/radeon/cik.c
5810
tmp = RREG32(RLC_CNTL);
sys/dev/pci/drm/radeon/cik.c
5819
orig = data = RREG32(RLC_CNTL);
sys/dev/pci/drm/radeon/cik.c
5828
if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)
sys/dev/pci/drm/radeon/cik.c
5848
if ((RREG32(RLC_GPM_STAT) & mask) == mask)
sys/dev/pci/drm/radeon/cik.c
5854
if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
sys/dev/pci/drm/radeon/cik.c
5919
tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
sys/dev/pci/drm/radeon/cik.c
5994
orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
sys/dev/pci/drm/radeon/cik.c
6013
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/cik.c
6014
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/cik.c
6015
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/cik.c
6016
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/cik.c
6033
orig = data = RREG32(CP_MEM_SLP_CNTL);
sys/dev/pci/drm/radeon/cik.c
6040
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/radeon/cik.c
6057
orig = data = RREG32(CGTS_SM_CTRL_REG);
sys/dev/pci/drm/radeon/cik.c
6072
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/radeon/cik.c
6077
data = RREG32(RLC_MEM_SLP_CNTL);
sys/dev/pci/drm/radeon/cik.c
6083
data = RREG32(CP_MEM_SLP_CNTL);
sys/dev/pci/drm/radeon/cik.c
6089
orig = data = RREG32(CGTS_SM_CTRL_REG);
sys/dev/pci/drm/radeon/cik.c
6126
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/pci/drm/radeon/cik.c
6143
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/pci/drm/radeon/cik.c
6162
orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
6167
orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
6180
orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
6185
orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
6190
orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
6195
orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
6212
orig = data = RREG32(UVD_CGC_CTRL);
sys/dev/pci/drm/radeon/cik.c
6221
orig = data = RREG32(UVD_CGC_CTRL);
sys/dev/pci/drm/radeon/cik.c
6251
orig = data = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/cik.c
6267
orig = data = RREG32(HDP_MEM_POWER_LS);
sys/dev/pci/drm/radeon/cik.c
6357
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/cik.c
6371
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/cik.c
6384
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/cik.c
6397
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/cik.c
6500
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/cik.c
6505
orig = data = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/pci/drm/radeon/cik.c
6510
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/cik.c
6515
orig = data = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/pci/drm/radeon/cik.c
6520
data = RREG32(DB_RENDER_CONTROL);
sys/dev/pci/drm/radeon/cik.c
6530
tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/radeon/cik.c
6531
tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/radeon/cik.c
6574
tmp = RREG32(RLC_MAX_PG_CU);
sys/dev/pci/drm/radeon/cik.c
6585
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/cik.c
6599
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/cik.c
6632
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/cik.c
6640
data = RREG32(CP_RB_WPTR_POLL_CNTL);
sys/dev/pci/drm/radeon/cik.c
6648
data = RREG32(RLC_PG_DELAY_2);
sys/dev/pci/drm/radeon/cik.c
6653
data = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/pci/drm/radeon/cik.c
6814
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/pci/drm/radeon/cik.c
6815
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/cik.c
6833
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/cik.c
6834
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/pci/drm/radeon/cik.c
6859
tmp = RREG32(CP_INT_CNTL_RING0) &
sys/dev/pci/drm/radeon/cik.c
6863
tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/cik.c
6865
tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/cik.c
6909
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6911
tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6913
tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6915
tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6917
tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6919
tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6959
interrupt_cntl = RREG32(INTERRUPT_CNTL);
sys/dev/pci/drm/radeon/cik.c
7037
cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
sys/dev/pci/drm/radeon/cik.c
7041
hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/pci/drm/radeon/cik.c
7042
hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/pci/drm/radeon/cik.c
7043
hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/pci/drm/radeon/cik.c
7044
hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/pci/drm/radeon/cik.c
7045
hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/pci/drm/radeon/cik.c
7046
hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/pci/drm/radeon/cik.c
7048
dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7049
dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7051
cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7052
cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7053
cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7054
cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7055
cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7056
cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7057
cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7058
cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/pci/drm/radeon/cik.c
7271
RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/cik.c
7289
rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
sys/dev/pci/drm/radeon/cik.c
7290
rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
sys/dev/pci/drm/radeon/cik.c
7291
rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
sys/dev/pci/drm/radeon/cik.c
7292
rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
sys/dev/pci/drm/radeon/cik.c
7293
rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
sys/dev/pci/drm/radeon/cik.c
7294
rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
sys/dev/pci/drm/radeon/cik.c
7295
rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
sys/dev/pci/drm/radeon/cik.c
7297
rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/pci/drm/radeon/cik.c
7299
rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/pci/drm/radeon/cik.c
7302
rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/pci/drm/radeon/cik.c
7304
rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/pci/drm/radeon/cik.c
7308
rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/pci/drm/radeon/cik.c
7310
rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/pci/drm/radeon/cik.c
7364
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7369
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7374
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7379
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7384
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7389
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7394
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7399
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7404
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7409
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7414
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7419
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7488
wptr = RREG32(IH_RB_WPTR);
sys/dev/pci/drm/radeon/cik.c
7499
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/cik.c
7889
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
sys/dev/pci/drm/radeon/cik.c
7898
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/pci/drm/radeon/cik.c
7899
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/radeon/cik.c
7900
mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
sys/dev/pci/drm/radeon/cik.c
8860
if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
sys/dev/pci/drm/radeon/cik.c
8893
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/cik.c
9352
wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/cik.c
9361
tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/cik.c
9421
clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/pci/drm/radeon/cik.c
9422
((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/pci/drm/radeon/cik_sdma.c
121
(void)RREG32(reg);
sys/dev/pci/drm/radeon/cik_sdma.c
263
rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
sys/dev/pci/drm/radeon/cik_sdma.c
277
(void)RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik_sdma.c
280
(void)RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik_sdma.c
313
value = RREG32(SDMA0_CNTL + reg_offset);
sys/dev/pci/drm/radeon/cik_sdma.c
345
me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
sys/dev/pci/drm/radeon/cik_sdma.c
75
rptr = RREG32(reg);
sys/dev/pci/drm/radeon/cik_sdma.c
99
return (RREG32(reg) & 0x3fffc) >> 2;
sys/dev/pci/drm/radeon/cypress_dpm.c
1041
RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
sys/dev/pci/drm/radeon/cypress_dpm.c
106
RREG32(GB_ADDR_CONFIG);
sys/dev/pci/drm/radeon/cypress_dpm.c
1112
if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)
sys/dev/pci/drm/radeon/cypress_dpm.c
1127
if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
sys/dev/pci/drm/radeon/cypress_dpm.c
1156
if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
sys/dev/pci/drm/radeon/cypress_dpm.c
1175
value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
sys/dev/pci/drm/radeon/cypress_dpm.c
1214
if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))
sys/dev/pci/drm/radeon/cypress_dpm.c
147
RREG32(GB_ADDR_CONFIG);
sys/dev/pci/drm/radeon/cypress_dpm.c
1579
u32 tmp = RREG32(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/cypress_dpm.c
1733
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/cypress_dpm.c
1750
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/pci/drm/radeon/cypress_dpm.c
1763
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/pci/drm/radeon/cypress_dpm.c
505
mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
sys/dev/pci/drm/radeon/cypress_dpm.c
59
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/pci/drm/radeon/cypress_dpm.c
720
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/pci/drm/radeon/cypress_dpm.c
721
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/cypress_dpm.c
723
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/cypress_dpm.c
931
u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
155
dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
sys/dev/pci/drm/radeon/dce3_1_afmt.c
162
dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
sys/dev/pci/drm/radeon/dce6_afmt.c
306
unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
sys/dev/pci/drm/radeon/dce6_afmt.c
42
r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
sys/dev/pci/drm/radeon/evergreen.c
108
r = RREG32(EVERGREEN_PIF_PHY1_DATA);
sys/dev/pci/drm/radeon/evergreen.c
1104
*val = RREG32(reg);
sys/dev/pci/drm/radeon/evergreen.c
1156
if (RREG32(status_reg) & DCLK_STATUS)
sys/dev/pci/drm/radeon/evergreen.c
1169
u32 cg_scratch = RREG32(CG_SCRATCH1);
sys/dev/pci/drm/radeon/evergreen.c
1350
if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
sys/dev/pci/drm/radeon/evergreen.c
1360
pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/pci/drm/radeon/evergreen.c
1361
pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/pci/drm/radeon/evergreen.c
1384
if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
sys/dev/pci/drm/radeon/evergreen.c
1434
RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/evergreen.c
1450
return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &
sys/dev/pci/drm/radeon/evergreen.c
1461
toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
sys/dev/pci/drm/radeon/evergreen.c
1463
temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
sys/dev/pci/drm/radeon/evergreen.c
1474
temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
sys/dev/pci/drm/radeon/evergreen.c
1495
u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
sys/dev/pci/drm/radeon/evergreen.c
1685
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/evergreen.c
1710
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/evergreen.c
1731
return !!(RREG32(DC_HPDx_INT_STATUS_REG(hpd)) & DC_HPDx_SENSE);
sys/dev/pci/drm/radeon/evergreen.c
1876
if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
sys/dev/pci/drm/radeon/evergreen.c
1919
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/evergreen.c
2287
arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
sys/dev/pci/drm/radeon/evergreen.c
2296
tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
sys/dev/pci/drm/radeon/evergreen.c
2366
tmp = RREG32(SRBM_STATUS) & 0x1F00;
sys/dev/pci/drm/radeon/evergreen.c
2387
tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
sys/dev/pci/drm/radeon/evergreen.c
2579
dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2593
dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2600
dig_en_be = RREG32(NI_DIG_BE_EN_CNTL +
sys/dev/pci/drm/radeon/evergreen.c
2602
uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 +
sys/dev/pci/drm/radeon/evergreen.c
2635
stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
sys/dev/pci/drm/radeon/evergreen.c
2646
stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
sys/dev/pci/drm/radeon/evergreen.c
2651
stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
sys/dev/pci/drm/radeon/evergreen.c
2657
fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]);
sys/dev/pci/drm/radeon/evergreen.c
2670
save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
sys/dev/pci/drm/radeon/evergreen.c
2671
save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
sys/dev/pci/drm/radeon/evergreen.c
2678
crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
sys/dev/pci/drm/radeon/evergreen.c
2682
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2691
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2720
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2733
blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
2747
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2752
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2786
tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2791
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2796
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2802
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2811
tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
2820
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2826
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2897
tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
sys/dev/pci/drm/radeon/evergreen.c
3076
RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3079
RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3399
RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/evergreen.c
3403
mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/evergreen.c
3405
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/evergreen.c
3466
rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
sys/dev/pci/drm/radeon/evergreen.c
3487
simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
sys/dev/pci/drm/radeon/evergreen.c
3538
sx_debug_1 = RREG32(SX_DEBUG_1);
sys/dev/pci/drm/radeon/evergreen.c
3543
smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
sys/dev/pci/drm/radeon/evergreen.c
3569
sq_config = RREG32(SQ_CONFIG);
sys/dev/pci/drm/radeon/evergreen.c
3594
sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
sys/dev/pci/drm/radeon/evergreen.c
3696
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
3700
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
3719
tmp = RREG32(FUS_MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/evergreen.c
3721
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/evergreen.c
3729
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/evergreen.c
3754
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/evergreen.c
3755
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/evergreen.c
3758
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/pci/drm/radeon/evergreen.c
3759
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/pci/drm/radeon/evergreen.c
3771
RREG32(GRBM_STATUS));
sys/dev/pci/drm/radeon/evergreen.c
3773
RREG32(GRBM_STATUS_SE0));
sys/dev/pci/drm/radeon/evergreen.c
3775
RREG32(GRBM_STATUS_SE1));
sys/dev/pci/drm/radeon/evergreen.c
3777
RREG32(SRBM_STATUS));
sys/dev/pci/drm/radeon/evergreen.c
3779
RREG32(SRBM_STATUS2));
sys/dev/pci/drm/radeon/evergreen.c
3781
RREG32(CP_STALLED_STAT1));
sys/dev/pci/drm/radeon/evergreen.c
3783
RREG32(CP_STALLED_STAT2));
sys/dev/pci/drm/radeon/evergreen.c
3785
RREG32(CP_BUSY_STAT));
sys/dev/pci/drm/radeon/evergreen.c
3787
RREG32(CP_STAT));
sys/dev/pci/drm/radeon/evergreen.c
3789
RREG32(DMA_STATUS_REG));
sys/dev/pci/drm/radeon/evergreen.c
3792
RREG32(DMA_STATUS_REG + 0x800));
sys/dev/pci/drm/radeon/evergreen.c
3803
if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
sys/dev/pci/drm/radeon/evergreen.c
3804
crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
3812
tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
3831
tmp = RREG32(GRBM_STATUS);
sys/dev/pci/drm/radeon/evergreen.c
3847
tmp = RREG32(DMA_STATUS_REG);
sys/dev/pci/drm/radeon/evergreen.c
3852
tmp = RREG32(SRBM_STATUS2);
sys/dev/pci/drm/radeon/evergreen.c
3857
tmp = RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/evergreen.c
3881
tmp = RREG32(VM_L2_STATUS);
sys/dev/pci/drm/radeon/evergreen.c
3912
tmp = RREG32(DMA_RB_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
3972
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3976
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3982
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3986
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3990
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3996
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
4021
tmp = RREG32(DMA_RB_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
4044
if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
sys/dev/pci/drm/radeon/evergreen.c
4397
u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
sys/dev/pci/drm/radeon/evergreen.c
4454
return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
sys/dev/pci/drm/radeon/evergreen.c
4467
tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/evergreen.c
4471
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/evergreen.c
4512
thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) &
sys/dev/pci/drm/radeon/evergreen.c
4515
thermal_int = RREG32(CG_THERMAL_INT) &
sys/dev/pci/drm/radeon/evergreen.c
4518
dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/evergreen.c
4548
dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/evergreen.c
4605
RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/evergreen.c
4619
disp_int[i] = RREG32(evergreen_disp_int_status[i]);
sys/dev/pci/drm/radeon/evergreen.c
4620
afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
4622
grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
4682
wptr = RREG32(IH_RB_WPTR);
sys/dev/pci/drm/radeon/evergreen.c
4693
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
4837
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
sys/dev/pci/drm/radeon/evergreen.c
4846
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/pci/drm/radeon/evergreen.c
4847
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/radeon/evergreen.c
64
r = RREG32(EVERGREEN_CG_IND_DATA);
sys/dev/pci/drm/radeon/evergreen.c
86
r = RREG32(EVERGREEN_PIF_PHY0_DATA);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
251
value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
277
value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
295
unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &
sys/dev/pci/drm/radeon/evergreen_hdmi.c
326
val = RREG32(HDMI_CONTROL + offset);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
43
u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
467
val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
sys/dev/pci/drm/radeon/kv_dpm.c
179
data = RREG32(config_regs->offset << 2);
sys/dev/pci/drm/radeon/kv_smc.c
138
original_data = RREG32(SMC_IND_DATA_0);
sys/dev/pci/drm/radeon/kv_smc.c
192
original_data = RREG32(SMC_IND_DATA_0);
sys/dev/pci/drm/radeon/kv_smc.c
37
if ((RREG32(SMC_RESP_0) & SMC_RESP_MASK) != 0)
sys/dev/pci/drm/radeon/kv_smc.c
41
tmp = RREG32(SMC_RESP_0) & SMC_RESP_MASK;
sys/dev/pci/drm/radeon/kv_smc.c
97
*value = RREG32(SMC_IND_DATA_0);
sys/dev/pci/drm/radeon/ni.c
1071
rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
sys/dev/pci/drm/radeon/ni.c
1091
simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
sys/dev/pci/drm/radeon/ni.c
1140
cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
sys/dev/pci/drm/radeon/ni.c
1148
sx_debug_1 = RREG32(SX_DEBUG_1);
sys/dev/pci/drm/radeon/ni.c
1152
smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
sys/dev/pci/drm/radeon/ni.c
1214
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/pci/drm/radeon/ni.c
1218
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/ni.c
1337
rdev->vm_manager.saved_table_addr[i] = RREG32(
sys/dev/pci/drm/radeon/ni.c
1457
rptr = RREG32(CP_RB0_RPTR);
sys/dev/pci/drm/radeon/ni.c
1459
rptr = RREG32(CP_RB1_RPTR);
sys/dev/pci/drm/radeon/ni.c
1461
rptr = RREG32(CP_RB2_RPTR);
sys/dev/pci/drm/radeon/ni.c
1473
wptr = RREG32(CP_RB0_WPTR);
sys/dev/pci/drm/radeon/ni.c
1475
wptr = RREG32(CP_RB1_WPTR);
sys/dev/pci/drm/radeon/ni.c
1477
wptr = RREG32(CP_RB2_WPTR);
sys/dev/pci/drm/radeon/ni.c
1487
(void)RREG32(CP_RB0_WPTR);
sys/dev/pci/drm/radeon/ni.c
1490
(void)RREG32(CP_RB1_WPTR);
sys/dev/pci/drm/radeon/ni.c
1493
(void)RREG32(CP_RB2_WPTR);
sys/dev/pci/drm/radeon/ni.c
1645
RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1648
RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1726
tmp = RREG32(GRBM_STATUS);
sys/dev/pci/drm/radeon/ni.c
1743
tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni.c
1748
tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni.c
1753
tmp = RREG32(SRBM_STATUS2);
sys/dev/pci/drm/radeon/ni.c
1761
tmp = RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/ni.c
1785
tmp = RREG32(VM_L2_STATUS);
sys/dev/pci/drm/radeon/ni.c
1811
RREG32(0x14F8));
sys/dev/pci/drm/radeon/ni.c
1813
RREG32(0x14D8));
sys/dev/pci/drm/radeon/ni.c
1815
RREG32(0x14FC));
sys/dev/pci/drm/radeon/ni.c
1817
RREG32(0x14DC));
sys/dev/pci/drm/radeon/ni.c
1824
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni.c
1831
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni.c
1894
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1898
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1904
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1908
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1912
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1918
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
2484
u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
sys/dev/pci/drm/radeon/ni.c
2703
if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
sys/dev/pci/drm/radeon/ni.c
2713
if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
sys/dev/pci/drm/radeon/ni.c
54
r = RREG32(TN_SMC_IND_DATA_0);
sys/dev/pci/drm/radeon/ni.c
652
mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
sys/dev/pci/drm/radeon/ni.c
653
running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
sys/dev/pci/drm/radeon/ni.c
677
if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
sys/dev/pci/drm/radeon/ni.c
847
*val = RREG32(reg);
sys/dev/pci/drm/radeon/ni.c
993
RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/ni.c
994
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/ni_dma.c
165
rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni_dma.c
170
rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni_dma.c
238
dma_cntl = RREG32(DMA_CNTL + reg_offset);
sys/dev/pci/drm/radeon/ni_dma.c
65
rptr = RREG32(reg);
sys/dev/pci/drm/radeon/ni_dma.c
89
return (RREG32(reg) & 0x3fffc) >> 2;
sys/dev/pci/drm/radeon/ni_dpm.c
1086
tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
1183
ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/ni_dpm.c
1184
ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/ni_dpm.c
1185
ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/pci/drm/radeon/ni_dpm.c
1186
ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
sys/dev/pci/drm/radeon/ni_dpm.c
1187
ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/pci/drm/radeon/ni_dpm.c
1188
ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/pci/drm/radeon/ni_dpm.c
1189
ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/pci/drm/radeon/ni_dpm.c
1190
ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/ni_dpm.c
1191
ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/pci/drm/radeon/ni_dpm.c
1192
ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/ni_dpm.c
1193
ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/ni_dpm.c
1194
ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
sys/dev/pci/drm/radeon/ni_dpm.c
1195
ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/pci/drm/radeon/ni_dpm.c
1196
ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/pci/drm/radeon/ni_dpm.c
1208
RREG32(GB_ADDR_CONFIG);
sys/dev/pci/drm/radeon/ni_dpm.c
1367
u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
1514
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/radeon/ni_dpm.c
1515
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/radeon/ni_dpm.c
1516
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
sys/dev/pci/drm/radeon/ni_dpm.c
1519
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
sys/dev/pci/drm/radeon/ni_dpm.c
1520
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
sys/dev/pci/drm/radeon/ni_dpm.c
1521
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
sys/dev/pci/drm/radeon/ni_dpm.c
1524
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
sys/dev/pci/drm/radeon/ni_dpm.c
1525
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
sys/dev/pci/drm/radeon/ni_dpm.c
1526
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
sys/dev/pci/drm/radeon/ni_dpm.c
1529
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
sys/dev/pci/drm/radeon/ni_dpm.c
1530
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
sys/dev/pci/drm/radeon/ni_dpm.c
1531
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
sys/dev/pci/drm/radeon/ni_dpm.c
1562
mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
sys/dev/pci/drm/radeon/ni_dpm.c
1626
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/radeon/ni_dpm.c
1627
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/radeon/ni_dpm.c
2189
mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
sys/dev/pci/drm/radeon/ni_dpm.c
2323
u32 tmp = RREG32(DC_STUTTER_CNTL);
sys/dev/pci/drm/radeon/ni_dpm.c
2350
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/pci/drm/radeon/ni_dpm.c
2351
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ni_dpm.c
2353
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/ni_dpm.c
2726
temp_reg = RREG32(MC_PMG_CMD_EMRS);
sys/dev/pci/drm/radeon/ni_dpm.c
2737
temp_reg = RREG32(MC_PMG_CMD_MRS);
sys/dev/pci/drm/radeon/ni_dpm.c
2752
temp_reg = RREG32(MC_PMG_CMD_MRS1);
sys/dev/pci/drm/radeon/ni_dpm.c
2886
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/radeon/ni_dpm.c
2887
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/radeon/ni_dpm.c
2888
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/radeon/ni_dpm.c
2889
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/radeon/ni_dpm.c
2890
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/radeon/ni_dpm.c
2891
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/radeon/ni_dpm.c
2892
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/radeon/ni_dpm.c
2893
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/radeon/ni_dpm.c
2894
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/radeon/ni_dpm.c
2895
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/radeon/ni_dpm.c
2896
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/radeon/ni_dpm.c
2897
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/pci/drm/radeon/ni_dpm.c
2898
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/pci/drm/radeon/ni_dpm.c
3154
reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK);
sys/dev/pci/drm/radeon/ni_dpm.c
3354
reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3470
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
3485
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
4312
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/ni_dpm.c
4332
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/ni_dpm.c
4350
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/r100.c
101
vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/pci/drm/radeon/r100.c
102
vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/pci/drm/radeon/r100.c
1101
rptr = RREG32(RADEON_CP_RB_RPTR);
sys/dev/pci/drm/radeon/r100.c
1109
return RREG32(RADEON_CP_RB_WPTR);
sys/dev/pci/drm/radeon/r100.c
1116
(void)RREG32(RADEON_CP_RB_WPTR);
sys/dev/pci/drm/radeon/r100.c
126
if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
sys/dev/pci/drm/radeon/r100.c
129
if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
sys/dev/pci/drm/radeon/r100.c
185
if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
sys/dev/pci/drm/radeon/r100.c
211
return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
sys/dev/pci/drm/radeon/r100.c
2505
tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
sys/dev/pci/drm/radeon/r100.c
2523
tmp = RREG32(RADEON_RBBM_STATUS);
sys/dev/pci/drm/radeon/r100.c
2539
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/pci/drm/radeon/r100.c
2552
rbbm_status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r100.c
2565
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
sys/dev/pci/drm/radeon/r100.c
2574
tmp = RREG32(R_000030_BUS_CNTL);
sys/dev/pci/drm/radeon/r100.c
2580
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/pci/drm/radeon/r100.c
2592
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r100.c
2597
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r100.c
2601
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/pci/drm/radeon/r100.c
2614
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r100.c
2618
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r100.c
2622
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r100.c
2626
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r100.c
2687
u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
sys/dev/pci/drm/radeon/r100.c
2688
u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/r100.c
2689
u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
sys/dev/pci/drm/radeon/r100.c
2735
else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
sys/dev/pci/drm/radeon/r100.c
2740
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/pci/drm/radeon/r100.c
2751
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/pci/drm/radeon/r100.c
2768
aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
sys/dev/pci/drm/radeon/r100.c
2796
if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
sys/dev/pci/drm/radeon/r100.c
2812
config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
sys/dev/pci/drm/radeon/r100.c
2816
tom = RREG32(RADEON_NB_TOM);
sys/dev/pci/drm/radeon/r100.c
2821
rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/r100.c
2846
temp = RREG32(RADEON_CONFIG_CNTL);
sys/dev/pci/drm/radeon/r100.c
2864
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
sys/dev/pci/drm/radeon/r100.c
2879
(void)RREG32(RADEON_CLOCK_CNTL_DATA);
sys/dev/pci/drm/radeon/r100.c
2880
(void)RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
2901
save = RREG32(RADEON_CLOCK_CNTL_INDEX);
sys/dev/pci/drm/radeon/r100.c
2904
tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
sys/dev/pci/drm/radeon/r100.c
2917
data = RREG32(RADEON_CLOCK_CNTL_DATA);
sys/dev/pci/drm/radeon/r100.c
2958
seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
sys/dev/pci/drm/radeon/r100.c
2959
seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
sys/dev/pci/drm/radeon/r100.c
2960
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
sys/dev/pci/drm/radeon/r100.c
2963
reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
sys/dev/pci/drm/radeon/r100.c
2965
value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
sys/dev/pci/drm/radeon/r100.c
2979
rdp = RREG32(RADEON_CP_RB_RPTR);
sys/dev/pci/drm/radeon/r100.c
2980
wdp = RREG32(RADEON_CP_RB_WPTR);
sys/dev/pci/drm/radeon/r100.c
2982
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
sys/dev/pci/drm/radeon/r100.c
3004
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
sys/dev/pci/drm/radeon/r100.c
3005
seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
sys/dev/pci/drm/radeon/r100.c
3006
csq_stat = RREG32(RADEON_CP_CSQ_STAT);
sys/dev/pci/drm/radeon/r100.c
3007
csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
sys/dev/pci/drm/radeon/r100.c
3027
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/pci/drm/radeon/r100.c
3033
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/pci/drm/radeon/r100.c
3039
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/pci/drm/radeon/r100.c
3050
tmp = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/r100.c
3052
tmp = RREG32(RADEON_MC_FB_LOCATION);
sys/dev/pci/drm/radeon/r100.c
3054
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/pci/drm/radeon/r100.c
3056
tmp = RREG32(RADEON_MC_AGP_LOCATION);
sys/dev/pci/drm/radeon/r100.c
3058
tmp = RREG32(RADEON_AGP_BASE);
sys/dev/pci/drm/radeon/r100.c
3060
tmp = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/r100.c
3062
tmp = RREG32(0x01D0);
sys/dev/pci/drm/radeon/r100.c
3064
tmp = RREG32(RADEON_AIC_LO_ADDR);
sys/dev/pci/drm/radeon/r100.c
3066
tmp = RREG32(RADEON_AIC_HI_ADDR);
sys/dev/pci/drm/radeon/r100.c
3068
tmp = RREG32(0x01E4);
sys/dev/pci/drm/radeon/r100.c
3266
uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
sys/dev/pci/drm/radeon/r100.c
3312
temp = RREG32(RADEON_MEM_TIMING_CNTL);
sys/dev/pci/drm/radeon/r100.c
3352
temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/pci/drm/radeon/r100.c
3373
temp = RREG32(RADEON_MEM_CNTL);
sys/dev/pci/drm/radeon/r100.c
3377
temp = RREG32(R300_MC_IND_INDEX);
sys/dev/pci/drm/radeon/r100.c
3381
temp = RREG32(R300_MC_IND_DATA);
sys/dev/pci/drm/radeon/r100.c
3384
temp = RREG32(R300_MC_READ_CNTL_AB);
sys/dev/pci/drm/radeon/r100.c
3388
temp = RREG32(R300_MC_READ_CNTL_AB);
sys/dev/pci/drm/radeon/r100.c
3524
temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
sys/dev/pci/drm/radeon/r100.c
3547
temp = RREG32(RS400_DISP1_REG_CNTL);
sys/dev/pci/drm/radeon/r100.c
3553
temp = RREG32(RS400_DMIF_MEM_CNTL1);
sys/dev/pci/drm/radeon/r100.c
3564
(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
sys/dev/pci/drm/radeon/r100.c
3580
grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
sys/dev/pci/drm/radeon/r100.c
3639
temp = RREG32(RS400_DISP2_REQ_CNTL1);
sys/dev/pci/drm/radeon/r100.c
3645
temp = RREG32(RS400_DISP2_REQ_CNTL2);
sys/dev/pci/drm/radeon/r100.c
3659
(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
sys/dev/pci/drm/radeon/r100.c
3693
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r100.c
371
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/r100.c
3770
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r100.c
380
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/r100.c
3800
save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
sys/dev/pci/drm/radeon/r100.c
3801
save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
3802
save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
sys/dev/pci/drm/radeon/r100.c
3804
save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
3805
save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
sys/dev/pci/drm/radeon/r100.c
3818
C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
sys/dev/pci/drm/radeon/r100.c
3938
rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/r100.c
3967
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/r100.c
3968
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/r100.c
4025
tmp = RREG32(RADEON_CP_CSQ_CNTL);
sys/dev/pci/drm/radeon/r100.c
4029
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/pci/drm/radeon/r100.c
4033
tmp = RREG32(RADEON_SCRATCH_UMSK);
sys/dev/pci/drm/radeon/r100.c
4071
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/r100.c
4072
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/r100.c
472
tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
476
tmp = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
503
tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
507
tmp = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
525
if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
sys/dev/pci/drm/radeon/r100.c
547
if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
sys/dev/pci/drm/radeon/r100.c
551
if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
sys/dev/pci/drm/radeon/r100.c
576
tmp = RREG32(RADEON_FP_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
584
tmp = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
676
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/pci/drm/radeon/r100.c
683
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
sys/dev/pci/drm/radeon/r100.c
698
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/pci/drm/radeon/r100.c
752
RREG32(RADEON_GEN_INT_CNTL);
sys/dev/pci/drm/radeon/r100.c
764
tmp = RREG32(R_000044_GEN_INT_STATUS);
sys/dev/pci/drm/radeon/r100.c
770
uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
sys/dev/pci/drm/radeon/r100.c
81
if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
sys/dev/pci/drm/radeon/r100.c
833
msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
sys/dev/pci/drm/radeon/r100.c
848
return RREG32(RADEON_CRTC_CRNT_FRAME);
sys/dev/pci/drm/radeon/r100.c
850
return RREG32(RADEON_CRTC2_CRNT_FRAME);
sys/dev/pci/drm/radeon/r100.c
86
if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
sys/dev/pci/drm/radeon/r100.c
98
vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/pci/drm/radeon/r100.c
984
tmp = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r100.c
99
vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/pci/drm/radeon/r300.c
1421
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/r300.c
1452
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/r300.c
1453
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/r300.c
1533
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/r300.c
1534
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/r300.c
341
(RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
sys/dev/pci/drm/radeon/r300.c
353
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/pci/drm/radeon/r300.c
398
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/r300.c
421
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r300.c
426
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r300.c
430
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/pci/drm/radeon/r300.c
441
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r300.c
445
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r300.c
453
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r300.c
457
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r300.c
482
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/pci/drm/radeon/r300.c
493
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
sys/dev/pci/drm/radeon/r300.c
67
r = RREG32(RADEON_PCIE_DATA);
sys/dev/pci/drm/radeon/r420.c
104
gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
sys/dev/pci/drm/radeon/r420.c
140
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/r420.c
144
RREG32(R300_RB2D_DSTCACHE_MODE) |
sys/dev/pci/drm/radeon/r420.c
153
tmp = RREG32(RV530_GB_PIPE_SELECT2);
sys/dev/pci/drm/radeon/r420.c
172
r = RREG32(R_0001FC_MC_IND_DATA);
sys/dev/pci/drm/radeon/r420.c
286
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/r420.c
318
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/r420.c
319
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/r420.c
409
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/r420.c
410
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/r420.c
481
tmp = RREG32(R400_GB_PIPE_SELECT);
sys/dev/pci/drm/radeon/r420.c
483
tmp = RREG32(R300_GB_TILE_CONFIG);
sys/dev/pci/drm/radeon/r420.c
485
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/r520.c
203
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/r520.c
232
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/r520.c
233
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/r520.c
278
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/r520.c
279
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/r520.c
82
gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
sys/dev/pci/drm/radeon/r520.c
83
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/r600.c
1099
tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
sys/dev/pci/drm/radeon/r600.c
1269
tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
sys/dev/pci/drm/radeon/r600.c
127
r = RREG32(R600_RCU_DATA);
sys/dev/pci/drm/radeon/r600.c
1284
r = RREG32(R_0028FC_MC_DATA);
sys/dev/pci/drm/radeon/r600.c
1424
base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
sys/dev/pci/drm/radeon/r600.c
1442
tmp = RREG32(RAMCFG);
sys/dev/pci/drm/radeon/r600.c
1450
tmp = RREG32(CHMAP);
sys/dev/pci/drm/radeon/r600.c
1471
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/r600.c
1472
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/r600.c
149
r = RREG32(R600_UVD_CTX_DATA);
sys/dev/pci/drm/radeon/r600.c
1556
u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
sys/dev/pci/drm/radeon/r600.c
1569
RREG32(R_008010_GRBM_STATUS));
sys/dev/pci/drm/radeon/r600.c
1571
RREG32(R_008014_GRBM_STATUS2));
sys/dev/pci/drm/radeon/r600.c
1573
RREG32(R_000E50_SRBM_STATUS));
sys/dev/pci/drm/radeon/r600.c
1575
RREG32(CP_STALLED_STAT1));
sys/dev/pci/drm/radeon/r600.c
1577
RREG32(CP_STALLED_STAT2));
sys/dev/pci/drm/radeon/r600.c
1579
RREG32(CP_BUSY_STAT));
sys/dev/pci/drm/radeon/r600.c
1581
RREG32(CP_STAT));
sys/dev/pci/drm/radeon/r600.c
1583
RREG32(DMA_STATUS_REG));
sys/dev/pci/drm/radeon/r600.c
1593
if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
sys/dev/pci/drm/radeon/r600.c
1594
crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/radeon/r600.c
1602
tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/radeon/r600.c
1621
tmp = RREG32(R_008010_GRBM_STATUS);
sys/dev/pci/drm/radeon/r600.c
1646
tmp = RREG32(DMA_STATUS_REG);
sys/dev/pci/drm/radeon/r600.c
1651
tmp = RREG32(R_000E50_SRBM_STATUS);
sys/dev/pci/drm/radeon/r600.c
1708
tmp = RREG32(DMA_RB_CNTL);
sys/dev/pci/drm/radeon/r600.c
1784
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1788
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1794
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1798
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1802
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1808
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
183
*val = RREG32(reg);
sys/dev/pci/drm/radeon/r600.c
1839
tmp = RREG32(DMA_RB_CNTL);
sys/dev/pci/drm/radeon/r600.c
1857
tmp = RREG32(BUS_CNTL);
sys/dev/pci/drm/radeon/r600.c
1861
tmp = RREG32(BIF_SCRATCH0);
sys/dev/pci/drm/radeon/r600.c
1875
if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
sys/dev/pci/drm/radeon/r600.c
2087
ramcfg = RREG32(RAMCFG);
sys/dev/pci/drm/radeon/r600.c
2119
cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
sys/dev/pci/drm/radeon/r600.c
2124
disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
sys/dev/pci/drm/radeon/r600.c
2159
tmp = RREG32(SX_DEBUG_1);
sys/dev/pci/drm/radeon/r600.c
2184
tmp = RREG32(SQ_MS_FIFO_SIZES);
sys/dev/pci/drm/radeon/r600.c
2203
sq_config = RREG32(SQ_CONFIG);
sys/dev/pci/drm/radeon/r600.c
2377
tmp = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/r600.c
2380
tmp = RREG32(ARB_POP);
sys/dev/pci/drm/radeon/r600.c
2402
(void)RREG32(PCIE_PORT_INDEX);
sys/dev/pci/drm/radeon/r600.c
2403
r = RREG32(PCIE_PORT_DATA);
sys/dev/pci/drm/radeon/r600.c
2414
(void)RREG32(PCIE_PORT_INDEX);
sys/dev/pci/drm/radeon/r600.c
2416
(void)RREG32(PCIE_PORT_DATA);
sys/dev/pci/drm/radeon/r600.c
2626
rptr = RREG32(R600_CP_RB_RPTR);
sys/dev/pci/drm/radeon/r600.c
2634
return RREG32(R600_CP_RB_WPTR);
sys/dev/pci/drm/radeon/r600.c
2641
(void)RREG32(R600_CP_RB_WPTR);
sys/dev/pci/drm/radeon/r600.c
2662
RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
2725
RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
2847
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r600.c
3194
temp = RREG32(CONFIG_CNTL);
sys/dev/pci/drm/radeon/r600.c
3436
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r600.c
352
u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
sys/dev/pci/drm/radeon/r600.c
3537
RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
3540
RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
3592
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/pci/drm/radeon/r600.c
3593
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/r600.c
3604
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/r600.c
3605
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/pci/drm/radeon/r600.c
3623
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/r600.c
3632
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3634
tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3636
tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3638
tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3641
tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3643
tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3645
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3647
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3650
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3652
tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3658
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3660
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3662
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3664
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3666
tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3698
interrupt_cntl = RREG32(INTERRUPT_CNTL);
sys/dev/pci/drm/radeon/r600.c
3784
hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/pci/drm/radeon/r600.c
3785
hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/pci/drm/radeon/r600.c
3786
hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/pci/drm/radeon/r600.c
3787
hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/pci/drm/radeon/r600.c
3789
hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/pci/drm/radeon/r600.c
3790
hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/pci/drm/radeon/r600.c
3791
hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3792
hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3794
hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3795
hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3798
hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/pci/drm/radeon/r600.c
3799
hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/pci/drm/radeon/r600.c
3800
hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/pci/drm/radeon/r600.c
3801
hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3802
hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3805
dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/r600.c
3808
thermal_int = RREG32(CG_THERMAL_INT) &
sys/dev/pci/drm/radeon/r600.c
3811
thermal_int = RREG32(RV770_CG_THERMAL_INT) &
sys/dev/pci/drm/radeon/r600.c
3907
RREG32(R_000E50_SRBM_STATUS);
sys/dev/pci/drm/radeon/r600.c
3917
rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
sys/dev/pci/drm/radeon/r600.c
3918
rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
sys/dev/pci/drm/radeon/r600.c
3919
rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
sys/dev/pci/drm/radeon/r600.c
3921
rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
sys/dev/pci/drm/radeon/r600.c
3922
rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
sys/dev/pci/drm/radeon/r600.c
3924
rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
sys/dev/pci/drm/radeon/r600.c
3925
rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
sys/dev/pci/drm/radeon/r600.c
3928
rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
sys/dev/pci/drm/radeon/r600.c
3929
rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
sys/dev/pci/drm/radeon/r600.c
3931
rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
sys/dev/pci/drm/radeon/r600.c
3932
rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
sys/dev/pci/drm/radeon/r600.c
3934
rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
sys/dev/pci/drm/radeon/r600.c
3935
rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
sys/dev/pci/drm/radeon/r600.c
3951
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3955
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3962
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3966
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3973
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3977
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3983
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3989
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3994
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3999
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
sys/dev/pci/drm/radeon/r600.c
4004
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
sys/dev/pci/drm/radeon/r600.c
4010
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
sys/dev/pci/drm/radeon/r600.c
4016
tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
sys/dev/pci/drm/radeon/r600.c
4020
tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
sys/dev/pci/drm/radeon/r600.c
4044
wptr = RREG32(IH_RB_WPTR);
sys/dev/pci/drm/radeon/r600.c
4055
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/r600.c
4107
RREG32(IH_RB_WPTR);
sys/dev/pci/drm/radeon/r600.c
4553
link_cntl2 = RREG32(0x4088);
sys/dev/pci/drm/radeon/r600.c
4567
tmp = RREG32(0x541c);
sys/dev/pci/drm/radeon/r600.c
4617
clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/pci/drm/radeon/r600.c
4618
((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/pci/drm/radeon/r600.c
797
if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
sys/dev/pci/drm/radeon/r600.c
811
if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/pci/drm/radeon/r600.c
815
if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/pci/drm/radeon/r600.c
819
if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/pci/drm/radeon/r600.c
823
if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/pci/drm/radeon/r600.c
828
if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/pci/drm/radeon/r600.c
832
if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/pci/drm/radeon/r600.c
841
if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
sys/dev/pci/drm/radeon/r600.c
845
if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
sys/dev/pci/drm/radeon/r600.c
849
if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
sys/dev/pci/drm/radeon/r600.c
868
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
876
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
884
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
892
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
900
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
909
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
922
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
930
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
938
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
sys/dev/pci/drm/radeon/r600_dma.c
100
u32 rb_cntl = RREG32(DMA_RB_CNTL);
sys/dev/pci/drm/radeon/r600_dma.c
159
dma_cntl = RREG32(DMA_CNTL);
sys/dev/pci/drm/radeon/r600_dma.c
58
rptr = RREG32(DMA_RB_RPTR);
sys/dev/pci/drm/radeon/r600_dma.c
74
return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;
sys/dev/pci/drm/radeon/r600_dpm.c
252
if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1)
sys/dev/pci/drm/radeon/r600_dpm.c
260
RREG32(GRBM_PWR_CNTL);
sys/dev/pci/drm/radeon/r600_dpm.c
295
if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
sys/dev/pci/drm/radeon/r600_dpm.c
330
if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)
sys/dev/pci/drm/radeon/r600_dpm.c
536
tmp = RREG32(VID_UPPER_GPIO_CNTL);
sys/dev/pci/drm/radeon/r600_dpm.c
546
gpio = RREG32(GPIOPAD_MASK);
sys/dev/pci/drm/radeon/r600_dpm.c
550
gpio = RREG32(GPIOPAD_EN);
sys/dev/pci/drm/radeon/r600_dpm.c
554
gpio = RREG32(GPIOPAD_A);
sys/dev/pci/drm/radeon/r600_dpm.c
626
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK;
sys/dev/pci/drm/radeon/r600_dpm.c
635
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK;
sys/dev/pci/drm/radeon/r600_hdmi.c
101
value = RREG32(R600_AUDIO_STATUS_BITS);
sys/dev/pci/drm/radeon/r600_hdmi.c
146
u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
sys/dev/pci/drm/radeon/r600_hdmi.c
271
return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
sys/dev/pci/drm/radeon/r600_hdmi.c
427
value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
sys/dev/pci/drm/radeon/r600_hdmi.c
65
value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
sys/dev/pci/drm/radeon/radeon.h
2582
uint32_t tmp_ = RREG32(reg); \
sys/dev/pci/drm/radeon/radeon_agp.c
280
agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
sys/dev/pci/drm/radeon/radeon_agp.c
374
WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);
sys/dev/pci/drm/radeon/radeon_atombios.c
4088
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4089
bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4091
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4092
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4126
rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
sys/dev/pci/drm/radeon/radeon_atombios.c
4150
bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4152
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4182
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4183
bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4184
bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4186
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4187
bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4188
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4367
bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4369
bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4422
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
sys/dev/pci/drm/radeon/radeon_atombios.c
4424
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
sys/dev/pci/drm/radeon/radeon_audio.c
59
return RREG32(reg);
sys/dev/pci/drm/radeon/radeon_bios.c
399
bus_cntl = RREG32(R600_BUS_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
400
d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
401
d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
402
vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
403
rom_cntl = RREG32(R600_ROM_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
445
viph_control = RREG32(RADEON_VIPH_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
446
bus_cntl = RREG32(R600_BUS_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
447
d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
448
d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
449
vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
450
rom_cntl = RREG32(R600_ROM_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
467
cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
476
cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
sys/dev/pci/drm/radeon/radeon_bios.c
491
cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
sys/dev/pci/drm/radeon/radeon_bios.c
528
viph_control = RREG32(RADEON_VIPH_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
529
bus_cntl = RREG32(R600_BUS_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
530
d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
531
d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
532
vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
533
rom_cntl = RREG32(R600_ROM_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
534
general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/radeon_bios.c
535
low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
536
medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
537
high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
538
ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
539
lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
sys/dev/pci/drm/radeon/radeon_bios.c
602
seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
sys/dev/pci/drm/radeon/radeon_bios.c
603
viph_control = RREG32(RADEON_VIPH_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
604
bus_cntl = RREG32(RV370_BUS_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
605
d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
606
d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
607
vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
608
gpiopad_a = RREG32(RADEON_GPIOPAD_A);
sys/dev/pci/drm/radeon/radeon_bios.c
609
gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
sys/dev/pci/drm/radeon/radeon_bios.c
610
gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
sys/dev/pci/drm/radeon/radeon_bios.c
661
seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
sys/dev/pci/drm/radeon/radeon_bios.c
662
viph_control = RREG32(RADEON_VIPH_CONTROL);
sys/dev/pci/drm/radeon/radeon_bios.c
664
bus_cntl = RREG32(RV370_BUS_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
666
bus_cntl = RREG32(RADEON_BUS_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
667
crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
669
crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
673
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_bios.c
677
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
567
if ((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/pci/drm/radeon/radeon_clocks.c
706
if (RREG32(RADEON_MEM_CNTL) &
sys/dev/pci/drm/radeon/radeon_clocks.c
759
((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/pci/drm/radeon/radeon_clocks.c
764
((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/pci/drm/radeon/radeon_clocks.c
782
((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/pci/drm/radeon/radeon_clocks.c
794
((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/pci/drm/radeon/radeon_combios.c
1100
uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_combios.c
1107
fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
sys/dev/pci/drm/radeon/radeon_combios.c
1108
fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
sys/dev/pci/drm/radeon/radeon_combios.c
1114
lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_combios.c
1124
(RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
sys/dev/pci/drm/radeon/radeon_combios.c
1132
((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
sys/dev/pci/drm/radeon/radeon_combios.c
2919
val = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_combios.c
2973
val = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_combios.c
3040
tmp = RREG32(addr);
sys/dev/pci/drm/radeon/radeon_combios.c
3050
tmp = RREG32(addr);
sys/dev/pci/drm/radeon/radeon_combios.c
3075
if ((RREG32(RADEON_MC_STATUS) &
sys/dev/pci/drm/radeon/radeon_combios.c
3203
if ((RREG32(RADEON_MEM_STR_CNTL) &
sys/dev/pci/drm/radeon/radeon_combios.c
3212
tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/pci/drm/radeon/radeon_combios.c
3218
tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/pci/drm/radeon/radeon_combios.c
3236
mem_cntl = RREG32(RADEON_MEM_CNTL);
sys/dev/pci/drm/radeon/radeon_combios.c
3243
RREG32(RADEON_MEM_CNTL);
sys/dev/pci/drm/radeon/radeon_combios.c
3419
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
sys/dev/pci/drm/radeon/radeon_combios.c
3420
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_combios.c
3421
bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
sys/dev/pci/drm/radeon/radeon_combios.c
3444
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_combios.c
3464
uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
sys/dev/pci/drm/radeon/radeon_combios.c
3465
uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
sys/dev/pci/drm/radeon/radeon_combios.c
3563
uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
sys/dev/pci/drm/radeon/radeon_combios.c
3598
uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_cursor.c
39
cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/radeon_cursor.c
46
cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/radeon_cursor.c
53
cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/radeon_device.c
220
tmp = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_device.c
689
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
sys/dev/pci/drm/radeon/radeon_device.c
690
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/radeon_device.c
692
reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
sys/dev/pci/drm/radeon/radeon_device.c
693
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/radeon_device.c
696
reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
sys/dev/pci/drm/radeon/radeon_device.c
697
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/radeon_device.c
702
reg = RREG32(AVIVO_D1CRTC_CONTROL) |
sys/dev/pci/drm/radeon/radeon_device.c
703
RREG32(AVIVO_D2CRTC_CONTROL);
sys/dev/pci/drm/radeon/radeon_device.c
708
reg = RREG32(RADEON_CRTC_GEN_CNTL) |
sys/dev/pci/drm/radeon/radeon_device.c
709
RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_device.c
718
reg = RREG32(R600_CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/radeon_device.c
720
reg = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/radeon_device.c
933
r = RREG32(reg*4);
sys/dev/pci/drm/radeon/radeon_display.c
1828
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/pci/drm/radeon/radeon_display.c
1830
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/pci/drm/radeon/radeon_display.c
1835
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/pci/drm/radeon/radeon_display.c
1837
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/pci/drm/radeon/radeon_display.c
1842
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/pci/drm/radeon/radeon_display.c
1844
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/pci/drm/radeon/radeon_display.c
1849
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/pci/drm/radeon/radeon_display.c
1851
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/pci/drm/radeon/radeon_display.c
1856
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/pci/drm/radeon/radeon_display.c
1858
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/pci/drm/radeon/radeon_display.c
1863
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/pci/drm/radeon/radeon_display.c
1865
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/pci/drm/radeon/radeon_display.c
1871
vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
sys/dev/pci/drm/radeon/radeon_display.c
1872
position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
sys/dev/pci/drm/radeon/radeon_display.c
1876
vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
sys/dev/pci/drm/radeon/radeon_display.c
1877
position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
sys/dev/pci/drm/radeon/radeon_display.c
1886
vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
sys/dev/pci/drm/radeon/radeon_display.c
1889
position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/pci/drm/radeon/radeon_display.c
1890
stat_crtc = RREG32(RADEON_CRTC_STATUS);
sys/dev/pci/drm/radeon/radeon_display.c
1897
vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
sys/dev/pci/drm/radeon/radeon_display.c
1899
position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/pci/drm/radeon/radeon_display.c
1900
stat_crtc = RREG32(RADEON_CRTC2_STATUS);
sys/dev/pci/drm/radeon/radeon_display.c
202
dac2_cntl = RREG32(RADEON_DAC_CNTL2);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
104
tmp = RREG32(AUX_CONTROL + aux_offset[instance]);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
153
tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
181
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
185
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
99
tmp = RREG32(chan->rec.mask_clk_reg);
sys/dev/pci/drm/radeon/radeon_fence.c
99
seq = RREG32(drv->scratch_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
127
temp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
133
temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
136
temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
140
temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
143
temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
147
temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
149
temp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
151
temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
153
temp = RREG32(rec->mask_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
166
temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
168
temp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
170
temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
172
temp = RREG32(rec->mask_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
185
val = RREG32(rec->y_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
200
val = RREG32(rec->y_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
214
val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
227
val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
445
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_i2c.c
573
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
576
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
605
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
608
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
618
p->buf[j] = RREG32(i2c_data) & 0xff;
sys/dev/pci/drm/radeon/radeon_i2c.c
633
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
636
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
659
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_i2c.c
692
tmp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
695
tmp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
697
tmp = RREG32(rec->mask_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
700
tmp = RREG32(rec->mask_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
703
tmp = RREG32(rec->a_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
706
tmp = RREG32(rec->a_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
708
tmp = RREG32(rec->a_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
711
tmp = RREG32(rec->a_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
714
tmp = RREG32(rec->en_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
717
tmp = RREG32(rec->en_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
719
tmp = RREG32(rec->en_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
722
tmp = RREG32(rec->en_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
725
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_i2c.c
727
saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
sys/dev/pci/drm/radeon/radeon_i2c.c
728
saved2 = RREG32(0x494);
sys/dev/pci/drm/radeon/radeon_i2c.c
734
if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
sys/dev/pci/drm/radeon/radeon_i2c.c
781
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
784
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
823
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
826
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
837
p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
sys/dev/pci/drm/radeon/radeon_i2c.c
866
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
869
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
896
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_irq_kms.c
611
u32 tmp = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
538
gen_cntl_val = RREG32(gen_cntl_reg);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
655
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
675
disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
68
fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
688
crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
706
crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
71
fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
712
disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
103
lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1044
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1047
tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1049
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1050
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1163
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1207
gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1208
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1210
disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1212
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1215
disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1220
dac_cntl = RREG32(RADEON_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1225
gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1227
dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1253
dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1309
gpiopad_a = RREG32(RADEON_GPIOPAD_A);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1310
dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1311
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1312
dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1313
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1314
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1338
RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1349
RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1352
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1382
dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1383
tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1384
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1385
config_cntl = RREG32(RADEON_CONFIG_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1386
tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1418
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1448
gpio_monid = RREG32(RADEON_GPIO_MONID);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1449
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1450
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1451
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1452
disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1453
disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1454
disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1455
disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1456
disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1457
disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1458
crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1459
crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1460
crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1461
crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1463
tmp = RREG32(RADEON_GPIO_MONID);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1492
tmp = RREG32(RADEON_GPIO_MONID);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1579
crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1582
gpiopad_a = RREG32(RADEON_GPIOPAD_A);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1583
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1585
disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1587
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1589
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1590
dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1591
dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1645
if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1648
if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
198
lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
201
lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
208
lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
219
lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
289
backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
361
backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
417
backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
516
uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
517
uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
518
uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
591
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
595
dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
600
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
605
dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
624
dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
654
crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
655
dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
656
dac_cntl = RREG32(RADEON_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
657
dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
67
lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
696
if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
728
uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
787
tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
818
tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
828
fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
892
uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
95
disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
954
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
956
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
98
lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
284
WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
296
WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
314
tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
334
tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
340
return RREG32(RADEON_TV_HOST_READ_DATA);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
612
tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
654
tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
749
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_ring.c
307
ptr = RREG32(ring->rptr_save_reg);
sys/dev/pci/drm/radeon/radeon_ring.c
487
rptr_next = RREG32(ring->rptr_save_reg);
sys/dev/pci/drm/radeon/radeon_ttm.c
853
value = RREG32(RADEON_MM_DATA);
sys/dev/pci/drm/radeon/radeon_uvd.c
1027
if ((RREG32(cg_upll_func_cntl) & mask) == mask)
sys/dev/pci/drm/radeon/rs400.c
157
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
sys/dev/pci/drm/radeon/rs400.c
161
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
sys/dev/pci/drm/radeon/rs400.c
248
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/pci/drm/radeon/rs400.c
277
RREG32(RADEON_MC_STATUS));
sys/dev/pci/drm/radeon/rs400.c
291
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
sys/dev/pci/drm/radeon/rs400.c
305
r = RREG32(RS480_NB_MC_DATA);
sys/dev/pci/drm/radeon/rs400.c
328
tmp = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/rs400.c
330
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/pci/drm/radeon/rs400.c
343
tmp = RREG32(RS690_HDP_FB_LOCATION);
sys/dev/pci/drm/radeon/rs400.c
346
tmp = RREG32(RADEON_AGP_BASE);
sys/dev/pci/drm/radeon/rs400.c
348
tmp = RREG32(RS480_AGP_BASE_2);
sys/dev/pci/drm/radeon/rs400.c
350
tmp = RREG32(RADEON_MC_AGP_LOCATION);
sys/dev/pci/drm/radeon/rs400.c
457
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/rs400.c
487
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/rs400.c
488
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/rs400.c
561
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/rs400.c
562
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/rs600.c
1019
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/rs600.c
1053
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/rs600.c
1054
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/rs600.c
1128
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/rs600.c
1129
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/rs600.c
123
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rs600.c
144
if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
sys/dev/pci/drm/radeon/rs600.c
160
return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
sys/dev/pci/drm/radeon/rs600.c
238
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/rs600.c
247
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/rs600.c
333
tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rs600.c
351
tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rs600.c
366
tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
sys/dev/pci/drm/radeon/rs600.c
371
tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
sys/dev/pci/drm/radeon/rs600.c
389
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
397
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
468
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/rs600.c
474
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/rs600.c
478
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/pci/drm/radeon/rs600.c
490
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/pci/drm/radeon/rs600.c
494
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/rs600.c
498
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/pci/drm/radeon/rs600.c
502
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/rs600.c
506
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/pci/drm/radeon/rs600.c
510
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/rs600.c
575
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
sys/dev/pci/drm/radeon/rs600.c
64
if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
sys/dev/pci/drm/radeon/rs600.c
670
u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
sys/dev/pci/drm/radeon/rs600.c
672
u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
sys/dev/pci/drm/radeon/rs600.c
676
hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
sys/dev/pci/drm/radeon/rs600.c
714
RREG32(R_000040_GEN_INT_CNTL);
sys/dev/pci/drm/radeon/rs600.c
721
uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
sys/dev/pci/drm/radeon/rs600.c
726
rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
sys/dev/pci/drm/radeon/rs600.c
736
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
74
pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/pci/drm/radeon/rs600.c
741
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
75
pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/pci/drm/radeon/rs600.c
750
rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
sys/dev/pci/drm/radeon/rs600.c
753
tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
768
u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
sys/dev/pci/drm/radeon/rs600.c
839
msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
sys/dev/pci/drm/radeon/rs600.c
854
return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
sys/dev/pci/drm/radeon/rs600.c
856
return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
sys/dev/pci/drm/radeon/rs600.c
887
rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/rs600.c
919
d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
sys/dev/pci/drm/radeon/rs600.c
920
d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
sys/dev/pci/drm/radeon/rs600.c
938
r = RREG32(R_000074_MC_IND_DATA);
sys/dev/pci/drm/radeon/rs600.c
98
if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
sys/dev/pci/drm/radeon/rs690.c
159
rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/rs690.c
228
tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
sys/dev/pci/drm/radeon/rs690.c
658
r = RREG32(R_00007C_MC_DATA);
sys/dev/pci/drm/radeon/rs690.c
730
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/rs690.c
764
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/rs690.c
765
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/rs690.c
840
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/rs690.c
841
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/rs780_dpm.c
1008
u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
sys/dev/pci/drm/radeon/rs780_dpm.c
1009
u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/rs780_dpm.c
212
u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
sys/dev/pci/drm/radeon/rs780_dpm.c
986
u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
sys/dev/pci/drm/radeon/rs780_dpm.c
987
u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/rv515.c
138
RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
sys/dev/pci/drm/radeon/rv515.c
150
gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
sys/dev/pci/drm/radeon/rv515.c
151
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/rv515.c
203
r = RREG32(MC_IND_DATA);
sys/dev/pci/drm/radeon/rv515.c
227
tmp = RREG32(GB_PIPE_SELECT);
sys/dev/pci/drm/radeon/rv515.c
229
tmp = RREG32(SU_REG_DEST);
sys/dev/pci/drm/radeon/rv515.c
231
tmp = RREG32(GB_TILE_CONFIG);
sys/dev/pci/drm/radeon/rv515.c
233
tmp = RREG32(DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/rv515.c
243
tmp = RREG32(0x2140);
sys/dev/pci/drm/radeon/rv515.c
246
tmp = RREG32(0x425C);
sys/dev/pci/drm/radeon/rv515.c
273
save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
sys/dev/pci/drm/radeon/rv515.c
274
save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
sys/dev/pci/drm/radeon/rv515.c
280
crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
sys/dev/pci/drm/radeon/rv515.c
283
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
301
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
316
blackout = RREG32(R700_MC_CITF_CNTL);
sys/dev/pci/drm/radeon/rv515.c
318
blackout = RREG32(R600_CITF_CNTL);
sys/dev/pci/drm/radeon/rv515.c
336
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
341
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
380
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
386
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
391
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
397
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
408
tmp = RREG32(R700_MC_CITF_CNTL);
sys/dev/pci/drm/radeon/rv515.c
410
tmp = RREG32(R600_CITF_CNTL);
sys/dev/pci/drm/radeon/rv515.c
422
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
523
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/rv515.c
552
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/rv515.c
553
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/rv515.c
632
RREG32(R_000E40_RBBM_STATUS),
sys/dev/pci/drm/radeon/rv515.c
633
RREG32(R_0007C0_CP_STAT));
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1182
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
2035
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/rv6xx_dpm.c
2060
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/rv6xx_dpm.c
2083
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/rv6xx_dpm.c
787
tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
789
dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3);
sys/dev/pci/drm/radeon/rv730_dpm.c
200
RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/rv730_dpm.c
202
RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv730_dpm.c
204
RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/pci/drm/radeon/rv730_dpm.c
206
RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/pci/drm/radeon/rv730_dpm.c
208
RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/pci/drm/radeon/rv730_dpm.c
211
RREG32(TCI_MCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/rv730_dpm.c
213
RREG32(TCI_DLL_CNTL);
sys/dev/pci/drm/radeon/rv730_dpm.c
215
RREG32(CG_MPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/rv730_dpm.c
217
RREG32(CG_MPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv730_dpm.c
219
RREG32(CG_MPLL_FUNC_CNTL_3);
sys/dev/pci/drm/radeon/rv730_dpm.c
221
RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM);
sys/dev/pci/drm/radeon/rv730_dpm.c
223
RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2);
sys/dev/pci/drm/radeon/rv730_dpm.c
400
arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) &
sys/dev/pci/drm/radeon/rv730_dpm.c
409
old_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/radeon/rv730_dpm.c
410
old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/radeon/rv730_dpm.c
416
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/radeon/rv730_dpm.c
417
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/radeon/rv730_dpm.c
426
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/radeon/rv730_dpm.c
427
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/radeon/rv730_dpm.c
436
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/radeon/rv730_dpm.c
437
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/radeon/rv730_dpm.c
479
mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
sys/dev/pci/drm/radeon/rv730_dpm.c
485
mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
sys/dev/pci/drm/radeon/rv730_dpm.c
500
mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
sys/dev/pci/drm/radeon/rv730_dpm.c
503
mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
sys/dev/pci/drm/radeon/rv740_dpm.c
292
RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/rv740_dpm.c
294
RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv740_dpm.c
296
RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/pci/drm/radeon/rv740_dpm.c
298
RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/pci/drm/radeon/rv740_dpm.c
300
RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/pci/drm/radeon/rv740_dpm.c
303
RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/pci/drm/radeon/rv740_dpm.c
305
RREG32(MPLL_AD_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv740_dpm.c
307
RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/pci/drm/radeon/rv740_dpm.c
309
RREG32(MPLL_DQ_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv740_dpm.c
311
RREG32(MCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/rv740_dpm.c
312
pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);
sys/dev/pci/drm/radeon/rv740_dpm.c
313
pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/pci/drm/radeon/rv740_dpm.c
314
pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/pci/drm/radeon/rv770.c
1022
tmp = RREG32(HDP_DEBUG1);
sys/dev/pci/drm/radeon/rv770.c
1106
RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/rv770.c
1142
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv770.c
1148
if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)
sys/dev/pci/drm/radeon/rv770.c
1156
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/pci/drm/radeon/rv770.c
1300
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/rv770.c
1302
shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
sys/dev/pci/drm/radeon/rv770.c
1316
cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
sys/dev/pci/drm/radeon/rv770.c
1338
disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
sys/dev/pci/drm/radeon/rv770.c
1403
ta_aux_cntl = RREG32(TA_CNTL_AUX);
sys/dev/pci/drm/radeon/rv770.c
1406
sx_debug_1 = RREG32(SX_DEBUG_1);
sys/dev/pci/drm/radeon/rv770.c
1410
smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
sys/dev/pci/drm/radeon/rv770.c
1424
db_debug3 = RREG32(DB_DEBUG3);
sys/dev/pci/drm/radeon/rv770.c
1440
db_debug4 = RREG32(DB_DEBUG4);
sys/dev/pci/drm/radeon/rv770.c
1480
sq_config = RREG32(SQ_CONFIG);
sys/dev/pci/drm/radeon/rv770.c
1593
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/rv770.c
1649
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/rv770.c
1657
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/rv770.c
1678
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/rv770.c
1679
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/rv770.c
2067
tmp = RREG32(0x541c);
sys/dev/pci/drm/radeon/rv770.c
789
u32 tmp = RREG32(CG_CLKPIN_CNTL);
sys/dev/pci/drm/radeon/rv770.c
804
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rv770.c
832
if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
sys/dev/pci/drm/radeon/rv770.c
848
return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
sys/dev/pci/drm/radeon/rv770.c
855
u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
sys/dev/pci/drm/radeon/rv770_dpm.c
1307
return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
sys/dev/pci/drm/radeon/rv770_dpm.c
1345
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
140
RREG32(GB_TILING_CONFIG);
sys/dev/pci/drm/radeon/rv770_dpm.c
1523
RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1525
RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv770_dpm.c
1527
RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/pci/drm/radeon/rv770_dpm.c
1529
RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/pci/drm/radeon/rv770_dpm.c
1531
RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/pci/drm/radeon/rv770_dpm.c
1533
RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1535
RREG32(MPLL_AD_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv770_dpm.c
1537
RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1539
RREG32(MPLL_DQ_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv770_dpm.c
1541
RREG32(MCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1542
pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1560
RREG32(S0_VID_LOWER_SMIO_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1569
(RREG32(GENERAL_PWRMGT) & SW_SMIO_INDEX_MASK) >> SW_SMIO_INDEX_SHIFT;
sys/dev/pci/drm/radeon/rv770_dpm.c
1572
vid_smio_cntl = RREG32(S3_VID_LOWER_SMIO_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1575
vid_smio_cntl = RREG32(S2_VID_LOWER_SMIO_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1578
vid_smio_cntl = RREG32(S1_VID_LOWER_SMIO_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1596
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/rv770_dpm.c
1637
RREG32(GB_TILING_CONFIG);
sys/dev/pci/drm/radeon/rv770_dpm.c
1659
if (((RREG32(SMC_MSG) & HOST_SMC_RESP_MASK) >> HOST_SMC_RESP_SHIFT) == 1)
sys/dev/pci/drm/radeon/rv770_dpm.c
172
if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
sys/dev/pci/drm/radeon/rv770_dpm.c
174
if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN)
sys/dev/pci/drm/radeon/rv770_dpm.c
208
if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
sys/dev/pci/drm/radeon/rv770_dpm.c
2474
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/rv770_dpm.c
2503
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/rv770_dpm.c
2525
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/rv770_dpm.c
731
tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/pci/drm/radeon/rv770_dpm.c
733
tmp = RREG32(MC_SEQ_MISC0) & 3;
sys/dev/pci/drm/radeon/rv770_dpm.c
881
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/rv770_smc.c
323
original_data = RREG32(SMC_SRAM_DATA);
sys/dev/pci/drm/radeon/rv770_smc.c
404
tmp = RREG32(SMC_IO);
sys/dev/pci/drm/radeon/rv770_smc.c
424
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;
sys/dev/pci/drm/radeon/rv770_smc.c
431
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;
sys/dev/pci/drm/radeon/rv770_smc.c
447
if (RREG32(SMC_IO) & SMC_STOP_MODE)
sys/dev/pci/drm/radeon/rv770_smc.c
600
*value = RREG32(SMC_SRAM_DATA);
sys/dev/pci/drm/radeon/si.c
1300
*val = RREG32(reg);
sys/dev/pci/drm/radeon/si.c
1323
tmp = RREG32(CG_CLKPIN_CNTL_2);
sys/dev/pci/drm/radeon/si.c
1327
tmp = RREG32(CG_CLKPIN_CNTL);
sys/dev/pci/drm/radeon/si.c
1340
temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
sys/dev/pci/drm/radeon/si.c
1603
running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
sys/dev/pci/drm/radeon/si.c
1635
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
sys/dev/pci/drm/radeon/si.c
1640
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
sys/dev/pci/drm/radeon/si.c
1756
if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
sys/dev/pci/drm/radeon/si.c
1986
if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
sys/dev/pci/drm/radeon/si.c
2008
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/si.c
2411
arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/si.c
2420
tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/si.c
2958
data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/radeon/si.c
2963
data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/radeon/si.c
2982
data = RREG32(SPI_STATIC_THREAD_MGMT_3);
sys/dev/pci/drm/radeon/si.c
3005
data = RREG32(CC_RB_BACKEND_DISABLE);
sys/dev/pci/drm/radeon/si.c
3010
data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
sys/dev/pci/drm/radeon/si.c
3184
RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/si.c
3185
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/si.c
3289
sx_debug_1 = RREG32(SX_DEBUG_1);
sys/dev/pci/drm/radeon/si.c
3323
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/pci/drm/radeon/si.c
3327
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/si.c
3760
tmp = RREG32(GRBM_STATUS);
sys/dev/pci/drm/radeon/si.c
3777
tmp = RREG32(GRBM_STATUS2);
sys/dev/pci/drm/radeon/si.c
3782
tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
3787
tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
3792
tmp = RREG32(SRBM_STATUS2);
sys/dev/pci/drm/radeon/si.c
3800
tmp = RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/si.c
3822
tmp = RREG32(VM_L2_STATUS);
sys/dev/pci/drm/radeon/si.c
3848
RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
sys/dev/pci/drm/radeon/si.c
3850
RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
sys/dev/pci/drm/radeon/si.c
3864
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
3870
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
3931
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3935
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3941
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3945
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3949
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3955
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3971
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/si.c
3975
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/si.c
3980
if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
sys/dev/pci/drm/radeon/si.c
3985
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/si.c
3989
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/pci/drm/radeon/si.c
3998
tmp = RREG32(SPLL_CNTL_MODE);
sys/dev/pci/drm/radeon/si.c
4002
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/si.c
4006
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/si.c
4010
tmp = RREG32(SPLL_CNTL_MODE);
sys/dev/pci/drm/radeon/si.c
4031
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
4035
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
4061
if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
sys/dev/pci/drm/radeon/si.c
4193
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/si.c
4201
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/si.c
4237
tmp = RREG32(CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/si.c
4363
rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
sys/dev/pci/drm/radeon/si.c
5113
if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
sys/dev/pci/drm/radeon/si.c
5119
if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
sys/dev/pci/drm/radeon/si.c
5128
u32 tmp = RREG32(CP_INT_CNTL_RING0);
sys/dev/pci/drm/radeon/si.c
5140
tmp = RREG32(DB_DEPTH_INFO);
sys/dev/pci/drm/radeon/si.c
5144
if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
sys/dev/pci/drm/radeon/si.c
5156
tmp = RREG32(UVD_CGC_CTRL);
sys/dev/pci/drm/radeon/si.c
5179
u32 tmp = RREG32(UVD_CGC_CTRL);
sys/dev/pci/drm/radeon/si.c
5189
orig = data = RREG32(RLC_CNTL);
sys/dev/pci/drm/radeon/si.c
5205
tmp = RREG32(RLC_CNTL);
sys/dev/pci/drm/radeon/si.c
5214
orig = data = RREG32(DMA_PG);
sys/dev/pci/drm/radeon/si.c
5243
tmp = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/si.c
5247
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/pci/drm/radeon/si.c
5251
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/pci/drm/radeon/si.c
5255
tmp = RREG32(DB_RENDER_CONTROL);
sys/dev/pci/drm/radeon/si.c
5265
tmp = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/si.c
5271
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/pci/drm/radeon/si.c
5285
tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/radeon/si.c
5286
tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/radeon/si.c
5329
tmp = RREG32(RLC_MAX_PG_CU);
sys/dev/pci/drm/radeon/si.c
5340
orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
sys/dev/pci/drm/radeon/si.c
5363
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/si.c
5364
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/si.c
5365
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/si.c
5366
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/si.c
5381
orig = data = RREG32(CGTS_SM_CTRL_REG);
sys/dev/pci/drm/radeon/si.c
5387
orig = data = RREG32(CP_MEM_SLP_CNTL);
sys/dev/pci/drm/radeon/si.c
5393
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/radeon/si.c
5406
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
sys/dev/pci/drm/radeon/si.c
5411
data = RREG32(CP_MEM_SLP_CNTL);
sys/dev/pci/drm/radeon/si.c
5416
orig = data = RREG32(CGTS_SM_CTRL_REG);
sys/dev/pci/drm/radeon/si.c
5441
orig = data = RREG32(UVD_CGC_CTRL);
sys/dev/pci/drm/radeon/si.c
5453
orig = data = RREG32(UVD_CGC_CTRL);
sys/dev/pci/drm/radeon/si.c
5483
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/pci/drm/radeon/si.c
5500
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/pci/drm/radeon/si.c
5522
orig = data = RREG32(DMA_POWER_CNTL + offset);
sys/dev/pci/drm/radeon/si.c
5534
orig = data = RREG32(DMA_POWER_CNTL + offset);
sys/dev/pci/drm/radeon/si.c
5539
orig = data = RREG32(DMA_CLK_CTRL + offset);
sys/dev/pci/drm/radeon/si.c
5570
orig = data = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/si.c
5586
orig = data = RREG32(HDP_MEM_POWER_LS);
sys/dev/pci/drm/radeon/si.c
5789
u32 tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
5822
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/si.c
5832
tmp = RREG32(RLC_LB_CNTL);
sys/dev/pci/drm/radeon/si.c
5902
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/pci/drm/radeon/si.c
5903
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/si.c
5914
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/si.c
5915
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/pci/drm/radeon/si.c
5933
tmp = RREG32(CP_INT_CNTL_RING0) &
sys/dev/pci/drm/radeon/si.c
5938
tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/si.c
5940
tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/si.c
5982
interrupt_cntl = RREG32(INTERRUPT_CNTL);
sys/dev/pci/drm/radeon/si.c
6051
cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
sys/dev/pci/drm/radeon/si.c
6054
dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/si.c
6055
dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/si.c
6057
thermal_int = RREG32(CG_THERMAL_INT) &
sys/dev/pci/drm/radeon/si.c
6119
RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/si.c
6135
disp_int[i] = RREG32(si_disp_int_status[i]);
sys/dev/pci/drm/radeon/si.c
6137
grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);
sys/dev/pci/drm/radeon/si.c
6197
wptr = RREG32(IH_RB_WPTR);
sys/dev/pci/drm/radeon/si.c
6208
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/si.c
6345
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
sys/dev/pci/drm/radeon/si.c
6354
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/pci/drm/radeon/si.c
6355
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/radeon/si.c
6971
clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/pci/drm/radeon/si.c
6972
((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/pci/drm/radeon/si.c
7373
orig = data = RREG32(THM_CLK_CNTL);
sys/dev/pci/drm/radeon/si.c
7379
orig = data = RREG32(MISC_CLK_CNTL);
sys/dev/pci/drm/radeon/si.c
7385
orig = data = RREG32(CG_CLKPIN_CNTL);
sys/dev/pci/drm/radeon/si.c
7390
orig = data = RREG32(CG_CLKPIN_CNTL_2);
sys/dev/pci/drm/radeon/si.c
7395
orig = data = RREG32(MPLL_BYPASSCLK_SEL);
sys/dev/pci/drm/radeon/si.c
7401
orig = data = RREG32(SPLL_CNTL_MODE);
sys/dev/pci/drm/radeon/si_dpm.c
2045
cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
2606
reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
2689
data = RREG32(config_regs->offset << 2);
sys/dev/pci/drm/radeon/si_dpm.c
3154
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/si_dpm.c
3160
width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
sys/dev/pci/drm/radeon/si_dpm.c
3162
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/si_dpm.c
3515
si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/si_dpm.c
3516
si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/si_dpm.c
3517
si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/pci/drm/radeon/si_dpm.c
3518
si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
sys/dev/pci/drm/radeon/si_dpm.c
3519
si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/pci/drm/radeon/si_dpm.c
3520
si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/pci/drm/radeon/si_dpm.c
3521
si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
sys/dev/pci/drm/radeon/si_dpm.c
3522
si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/si_dpm.c
3523
si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/pci/drm/radeon/si_dpm.c
3524
si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/pci/drm/radeon/si_dpm.c
3525
si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/si_dpm.c
3526
si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
sys/dev/pci/drm/radeon/si_dpm.c
3527
si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/si_dpm.c
3528
si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/pci/drm/radeon/si_dpm.c
3529
si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/pci/drm/radeon/si_dpm.c
3565
if (RREG32(SMC_RESP_0) == 1)
sys/dev/pci/drm/radeon/si_dpm.c
3629
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/pci/drm/radeon/si_dpm.c
3642
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/pci/drm/radeon/si_dpm.c
3743
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/si_dpm.c
4222
u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
4229
dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
sys/dev/pci/drm/radeon/si_dpm.c
4250
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/pci/drm/radeon/si_dpm.c
4251
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/pci/drm/radeon/si_dpm.c
4252
burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
4948
(RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
sys/dev/pci/drm/radeon/si_dpm.c
4967
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/pci/drm/radeon/si_dpm.c
4968
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/si_dpm.c
4970
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/si_dpm.c
4978
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/pci/drm/radeon/si_dpm.c
5311
temp_reg = RREG32(MC_PMG_CMD_EMRS);
sys/dev/pci/drm/radeon/si_dpm.c
5322
temp_reg = RREG32(MC_PMG_CMD_MRS);
sys/dev/pci/drm/radeon/si_dpm.c
5348
temp_reg = RREG32(MC_PMG_CMD_MRS1);
sys/dev/pci/drm/radeon/si_dpm.c
5488
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/pci/drm/radeon/si_dpm.c
5489
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/pci/drm/radeon/si_dpm.c
5490
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/pci/drm/radeon/si_dpm.c
5491
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/pci/drm/radeon/si_dpm.c
5492
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/pci/drm/radeon/si_dpm.c
5493
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/pci/drm/radeon/si_dpm.c
5494
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/pci/drm/radeon/si_dpm.c
5495
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/pci/drm/radeon/si_dpm.c
5496
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/pci/drm/radeon/si_dpm.c
5497
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/pci/drm/radeon/si_dpm.c
5498
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/pci/drm/radeon/si_dpm.c
5499
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/pci/drm/radeon/si_dpm.c
5500
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/pci/drm/radeon/si_dpm.c
5501
WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
sys/dev/pci/drm/radeon/si_dpm.c
5904
u32 thermal_int = RREG32(CG_THERMAL_INT);
sys/dev/pci/drm/radeon/si_dpm.c
5957
tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
5959
tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
5964
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
5968
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
5989
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
6033
tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
6088
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
6089
duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
6121
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
6130
tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6161
tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6178
tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
6207
tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6223
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6227
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6247
tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6252
tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
7043
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/si_dpm.c
7063
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/si_dpm.c
7081
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/pci/drm/radeon/si_smc.c
126
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/si_smc.c
127
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/si_smc.c
128
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/si_smc.c
129
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/pci/drm/radeon/si_smc.c
183
tmp = RREG32(SMC_RESP_0);
sys/dev/pci/drm/radeon/si_smc.c
188
tmp = RREG32(SMC_RESP_0);
sys/dev/pci/drm/radeon/si_smc.c
291
*value = RREG32(SMC_IND_DATA_0);
sys/dev/pci/drm/radeon/si_smc.c
86
original_data = RREG32(SMC_IND_DATA_0);
sys/dev/pci/drm/radeon/sumo_dpm.c
106
local0 = RREG32(CG_CGTT_LOCAL_0);
sys/dev/pci/drm/radeon/sumo_dpm.c
107
local1 = RREG32(CG_CGTT_LOCAL_1);
sys/dev/pci/drm/radeon/sumo_dpm.c
1745
u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
sys/dev/pci/drm/radeon/sumo_dpm.c
1822
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
sys/dev/pci/drm/radeon/sumo_dpm.c
1849
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
sys/dev/pci/drm/radeon/sumo_dpm.c
1877
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
sys/dev/pci/drm/radeon/sumo_dpm.c
278
RREG32(GB_ADDR_CONFIG);
sys/dev/pci/drm/radeon/sumo_dpm.c
497
u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
sys/dev/pci/drm/radeon/sumo_dpm.c
511
u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
sys/dev/pci/drm/radeon/sumo_dpm.c
521
u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
sys/dev/pci/drm/radeon/sumo_dpm.c
537
cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
sys/dev/pci/drm/radeon/sumo_dpm.c
550
u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
sys/dev/pci/drm/radeon/sumo_dpm.c
599
if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
sys/dev/pci/drm/radeon/sumo_dpm.c
629
if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
sys/dev/pci/drm/radeon/sumo_dpm.c
640
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
sys/dev/pci/drm/radeon/sumo_dpm.c
645
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
sys/dev/pci/drm/radeon/sumo_dpm.c
738
u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
sys/dev/pci/drm/radeon/sumo_dpm.c
800
u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
sys/dev/pci/drm/radeon/sumo_dpm.c
875
u32 v = RREG32(DOUT_SCRATCH3);
sys/dev/pci/drm/radeon/sumo_dpm.c
889
u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
sys/dev/pci/drm/radeon/sumo_dpm.c
890
u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
sys/dev/pci/drm/radeon/sumo_dpm.c
927
u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
sys/dev/pci/drm/radeon/sumo_dpm.c
94
RREG32(GB_ADDR_CONFIG);
sys/dev/pci/drm/radeon/sumo_dpm.c
940
u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
sys/dev/pci/drm/radeon/sumo_dpm.c
969
u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
sys/dev/pci/drm/radeon/sumo_smc.c
39
if (RREG32(GFX_INT_STATUS) & INT_DONE)
sys/dev/pci/drm/radeon/sumo_smc.c
48
if (RREG32(GFX_INT_REQ) & INT_REQ)
sys/dev/pci/drm/radeon/sumo_smc.c
54
if (RREG32(GFX_INT_STATUS) & INT_ACK)
sys/dev/pci/drm/radeon/sumo_smc.c
60
if (RREG32(GFX_INT_STATUS) & INT_DONE)
sys/dev/pci/drm/radeon/trinity_dpm.c
1991
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >>
sys/dev/pci/drm/radeon/trinity_dpm.c
2012
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >>
sys/dev/pci/drm/radeon/trinity_dpm.c
323
u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
sys/dev/pci/drm/radeon/trinity_dpm.c
403
RREG32(GB_ADDR_CONFIG);
sys/dev/pci/drm/radeon/trinity_dpm.c
464
RREG32(GB_ADDR_CONFIG);
sys/dev/pci/drm/radeon/trinity_dpm.c
725
if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN)
sys/dev/pci/drm/radeon/trinity_dpm.c
730
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_STATE_MASK) == 0)
sys/dev/pci/drm/radeon/trinity_dpm.c
735
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)
sys/dev/pci/drm/radeon/trinity_dpm.c
770
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)
sys/dev/pci/drm/radeon/trinity_dpm.c
891
u32 tmp = RREG32(CG_MISC_REG);
sys/dev/pci/drm/radeon/trinity_smc.c
117
if ((RREG32(SMC_INT_REQ) & 0xffff) == 1)
sys/dev/pci/drm/radeon/trinity_smc.c
36
if (RREG32(SMC_RESP_0) != 0)
sys/dev/pci/drm/radeon/trinity_smc.c
40
v = RREG32(SMC_RESP_0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
332
status = RREG32(UVD_STATUS);
sys/dev/pci/drm/radeon/uvd_v1_0.c
370
ring->wptr = RREG32(UVD_RBC_RB_RPTR);
sys/dev/pci/drm/radeon/uvd_v1_0.c
42
return RREG32(UVD_RBC_RB_RPTR);
sys/dev/pci/drm/radeon/uvd_v1_0.c
438
tmp = RREG32(UVD_CONTEXT_ID);
sys/dev/pci/drm/radeon/uvd_v1_0.c
56
return RREG32(UVD_RBC_RB_WPTR);
sys/dev/pci/drm/radeon/vce_v1_0.c
108
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/pci/drm/radeon/vce_v1_0.c
112
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
117
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
121
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/pci/drm/radeon/vce_v1_0.c
125
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
130
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
140
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/pci/drm/radeon/vce_v1_0.c
144
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v1_0.c
149
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
153
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
258
if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE)
sys/dev/pci/drm/radeon/vce_v1_0.c
265
if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS))
sys/dev/pci/drm/radeon/vce_v1_0.c
270
if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY))
sys/dev/pci/drm/radeon/vce_v1_0.c
328
status = RREG32(VCE_STATUS);
sys/dev/pci/drm/radeon/vce_v1_0.c
64
return RREG32(VCE_RB_RPTR);
sys/dev/pci/drm/radeon/vce_v1_0.c
66
return RREG32(VCE_RB_RPTR2);
sys/dev/pci/drm/radeon/vce_v1_0.c
81
return RREG32(VCE_RB_WPTR);
sys/dev/pci/drm/radeon/vce_v1_0.c
83
return RREG32(VCE_RB_WPTR2);
sys/dev/pci/drm/radeon/vce_v2_0.c
135
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/pci/drm/radeon/vce_v2_0.c
141
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
146
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v2_0.c
44
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v2_0.c
48
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
52
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
58
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v2_0.c
63
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
68
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
78
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v2_0.c
88
orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
94
orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);