sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2106

ENGINE_READ(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2107

ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1977

ENGINE_READ(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/intel_gt.c

146

intel_uncore_write(uncore, RING_CTL(base), 0);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

184

ENGINE_WRITE_FW(engine, RING_CTL, 0);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

185

ENGINE_POSTING_READ(engine, RING_CTL);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

263

ENGINE_WRITE_FW(engine, RING_CTL,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

268

RING_CTL(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

295

ENGINE_READ(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

296

ENGINE_READ(engine, RING_CTL) & RING_VALID,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

365

ENGINE_READ_FW(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

380

ENGINE_READ_FW(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

310

i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

70

{ RING_CTL(0), 0, 0, "CTL" }, \

sys/dev/pci/drm/i915/gvt/handlers.c

2244

MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);

sys/dev/pci/drm/i915/i915_gpu_error.c

1405

ee->ctl = ENGINE_READ(engine, RING_CTL);

sys/dev/pci/drm/i915/i915_pmu.c

362

val = ENGINE_READ_FW(engine, RING_CTL);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

94

MMIO_RING_D(RING_CTL);