sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2412

WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1750

data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1751

data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1799

data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1800

data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1809

WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/radeon/cik.c

5773

tmp = RREG32(RLC_LB_CNTL);

sys/dev/pci/drm/radeon/cik.c

5778

WREG32(RLC_LB_CNTL, tmp);

sys/dev/pci/drm/radeon/cik.c

5934

WREG32(RLC_LB_CNTL, 0x80000004);

sys/dev/pci/drm/radeon/si.c

5832

tmp = RREG32(RLC_LB_CNTL);

sys/dev/pci/drm/radeon/si.c

5837

WREG32(RLC_LB_CNTL, tmp);

sys/dev/pci/drm/radeon/si.c

5862

WREG32(RLC_LB_CNTL, 0);