RK3328_CRU_CLKSEL_CON
RK3328_CLK_RTC32K, RK3328_CRU_CLKSEL_CON(38),
RK3328_CLK_SPI, RK3328_CRU_CLKSEL_CON(24),
RK3328_CLK_SDMMC, RK3328_CRU_CLKSEL_CON(30),
RK3328_CLK_SDIO, RK3328_CRU_CLKSEL_CON(31),
RK3328_CLK_EMMC, RK3328_CRU_CLKSEL_CON(32),
RK3328_CLK_TSADC, RK3328_CRU_CLKSEL_CON(22),
RK3328_CLK_UART0, RK3328_CRU_CLKSEL_CON(14),
RK3328_CLK_UART1, RK3328_CRU_CLKSEL_CON(16),
RK3328_CLK_UART2, RK3328_CRU_CLKSEL_CON(18),
RK3328_CLK_WIFI, RK3328_CRU_CLKSEL_CON(52),
RK3328_CLK_I2C0, RK3328_CRU_CLKSEL_CON(34),
RK3328_CLK_I2C1, RK3328_CRU_CLKSEL_CON(34),
RK3328_CLK_I2C2, RK3328_CRU_CLKSEL_CON(35),
RK3328_CLK_I2C3, RK3328_CRU_CLKSEL_CON(35),
RK3328_CLK_CRYPTO, RK3328_CRU_CLKSEL_CON(20),
RK3328_CLK_PDM, RK3328_CRU_CLKSEL_CON(20),
RK3328_CLK_VDEC_CABAC, RK3328_CRU_CLKSEL_CON(48),
RK3328_CLK_VDEC_CORE, RK3328_CRU_CLKSEL_CON(49),
RK3328_CLK_VENC_DSP, RK3328_CRU_CLKSEL_CON(52),
RK3328_CLK_VENC_CORE, RK3328_CRU_CLKSEL_CON(51),
RK3328_CLK_TSP, RK3328_CRU_CLKSEL_CON(21),
RK3328_CLK_MAC2IO_SRC, RK3328_CRU_CLKSEL_CON(27),
RK3328_DCLK_LCDC, RK3328_CRU_CLKSEL_CON(40),
RK3328_ACLK_VOP_PRE, RK3328_CRU_CLKSEL_CON(39),
RK3328_ACLK_RGA_PRE, RK3328_CRU_CLKSEL_CON(36),
RK3328_ACLK_BUS_PRE, RK3328_CRU_CLKSEL_CON(0),
RK3328_ACLK_PERI_PRE, RK3328_CRU_CLKSEL_CON(28),
RK3328_ACLK_RKVDEC_PRE, RK3328_CRU_CLKSEL_CON(48),
RK3328_ACLK_RKVENC, RK3328_CRU_CLKSEL_CON(51),
RK3328_ACLK_VPU_PRE, RK3328_CRU_CLKSEL_CON(50),
RK3328_ACLK_VIO_PRE, RK3328_CRU_CLKSEL_CON(37),
RK3328_PCLK_BUS_PRE, RK3328_CRU_CLKSEL_CON(1),
RK3328_HCLK_BUS_PRE, RK3328_CRU_CLKSEL_CON(1),
RK3328_PCLK_PERI, RK3328_CRU_CLKSEL_CON(29),
RK3328_HCLK_PERI, RK3328_CRU_CLKSEL_CON(29),
RK3328_CLK_24M, RK3328_CRU_CLKSEL_CON(2),
reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(0));
reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(0));
HWRITE4(sc, RK3328_CRU_CLKSEL_CON(0),
HWRITE4(sc, RK3328_CRU_CLKSEL_CON(1),
HWRITE4(sc, RK3328_CRU_CLKSEL_CON(0),
HWRITE4(sc, RK3328_CRU_CLKSEL_CON(1),
reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(40));