RK3308_PLL_VPLL0
{ RK3308_PLL_VPLL0, RK3308_PLL_VPLL1 }
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1,
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1,
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1,
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1,
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1,
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1, 0 }
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1, 0 }
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1,
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1,
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1,
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1, 0 }
{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_PLL_VPLL1, 0 }
return RK3308_PLL_VPLL0;
pll = RK3308_PLL_VPLL0;
case RK3308_PLL_VPLL0:
case RK3308_PLL_VPLL0: