RK3308_CRU_CLKSEL_CON
RK3308_CLK_RTC32K, RK3308_CRU_CLKSEL_CON(2),
RK3308_CLK_UART0, RK3308_CRU_CLKSEL_CON(10),
RK3308_CLK_UART1, RK3308_CRU_CLKSEL_CON(13),
RK3308_CLK_UART2, RK3308_CRU_CLKSEL_CON(16),
RK3308_CLK_UART3, RK3308_CRU_CLKSEL_CON(19),
RK3308_CLK_UART4, RK3308_CRU_CLKSEL_CON(22),
RK3308_CLK_PWM0, RK3308_CRU_CLKSEL_CON(29),
RK3308_CLK_SPI0, RK3308_CRU_CLKSEL_CON(30),
RK3308_CLK_SPI1, RK3308_CRU_CLKSEL_CON(31),
RK3308_CLK_SPI2, RK3308_CRU_CLKSEL_CON(32),
RK3308_CLK_TSADC, RK3308_CRU_CLKSEL_CON(33),
RK3308_CLK_SARADC, RK3308_CRU_CLKSEL_CON(34),
RK3308_CLK_CRYPTO, RK3308_CRU_CLKSEL_CON(7),
RK3308_CLK_CRYPTO_APK, RK3308_CRU_CLKSEL_CON(7),
RK3308_CLK_SDMMC, RK3308_CRU_CLKSEL_CON(39),
RK3308_CLK_SDIO, RK3308_CRU_CLKSEL_CON(40),
RK3308_CLK_EMMC, RK3308_CRU_CLKSEL_CON(41),
RK3308_CLK_MAC_SRC, RK3308_CRU_CLKSEL_CON(43),
RK3308_CLK_MAC, RK3308_CRU_CLKSEL_CON(43),
RK3308_ACLK_PERI_SRC, RK3308_CRU_CLKSEL_CON(36),
RK3308_PCLK_PERI, RK3308_CRU_CLKSEL_CON(37),
reg = HREAD4(sc, RK3308_CRU_CLKSEL_CON(0));
reg = HREAD4(sc, RK3308_CRU_CLKSEL_CON(0));
HWRITE4(sc, RK3308_CRU_CLKSEL_CON(0),
HWRITE4(sc, RK3308_CRU_CLKSEL_CON(0),
reg = HREAD4(sc, RK3308_CRU_CLKSEL_CON(2));
div_con = HREAD4(sc, RK3308_CRU_CLKSEL_CON(4)) & 0xffff;
HWRITE4(sc, RK3308_CRU_CLKSEL_CON(2), 1 << 26 | (mux << 10));
HWRITE4(sc, RK3308_CRU_CLKSEL_CON(4), 0xffff0000 | div_con);