sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

104

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

105

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, trap_mask_bits);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

106

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

117

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, wave_launch_mode);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

140

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

145

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

150

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

46

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

47

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

48

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

60

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, keep_trap_enabled);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

61

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

62

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

155

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

185

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

329

data = REG_SET_FIELD(data, SQ_CONFIG, DISABLE_BARRIER_WAITCNT,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

121

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA_RLC0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

307

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

352

REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

354

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

369

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

370

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

371

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

415

ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

416

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

417

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

454

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

455

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

478

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

483

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

488

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

91

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA_RLC0_DOORBELL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1034

*reg_data = REG_SET_FIELD(*reg_data,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1039

*reg_data = REG_SET_FIELD(*reg_data,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

232

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

279

REG_SET_FIELD(m->cp_hqd_eop_rptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

282

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

405

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

435

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

688

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

690

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

692

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

741

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_VMID,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

766

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

768

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

847

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK, EXCP_EN, trap_mask_bits);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

848

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK, REPLACE, trap_override);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

870

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

872

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

905

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

909

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

913

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

919

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

923

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

927

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

933

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

941

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

965

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

973

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

203

value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

218

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

265

REG_SET_FIELD(m->cp_hqd_eop_rptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

268

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

391

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

421

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

600

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

602

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

604

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

188

value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

203

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

250

REG_SET_FIELD(m->cp_hqd_eop_rptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

253

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

376

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_QUEUE0_DOORBELL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

406

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_QUEUE0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

585

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

587

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

589

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

626

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

627

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

628

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

640

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

641

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

642

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

687

ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

688

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

689

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

723

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

724

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

735

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, wave_launch_mode);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

757

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

762

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

767

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

174

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

176

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

178

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

194

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

195

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

196

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

208

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

209

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

210

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

254

ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

255

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

256

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

291

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

292

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

306

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, STALL_VMID,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

309

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

332

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

337

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

342

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

182

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

196

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

265

data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

287

data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

178

value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

206

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

220

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

288

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

310

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

553

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

555

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

557

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1090

*reg_data = REG_SET_FIELD(*reg_data,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1095

*reg_data = REG_SET_FIELD(*reg_data,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1208

pipe_reset_data = REG_SET_FIELD(pipe_reset_data, CP_MEC_CNTL, MEC_ME1_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

246

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

291

REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

293

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

416

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

446

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

638

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

640

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

642

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

679

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_VMID,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

682

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

781

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK, EXCP_EN, trap_mask_bits);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

782

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK, REPLACE, trap_override);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

804

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

806

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

835

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

839

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

843

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

849

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

867

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

sys/dev/pci/drm/amd/amdgpu/cik.c

1900

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);

sys/dev/pci/drm/amd/amdgpu/cik.c

1901

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

373

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

382

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

121

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

123

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

130

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

131

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

132

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

135

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

149

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

152

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

206

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

216

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

222

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

378

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

65

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

66

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

84

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

85

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1126

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1129

tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1130

tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1133

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1136

tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1137

tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1220

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1257

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1259

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1262

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1264

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1310

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1313

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1316

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1319

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1389

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1391

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1393

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1405

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1486

tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1489

tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1493

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1496

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1500

tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1503

tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1551

tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1595

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1607

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1608

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1613

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1614

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1619

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1620

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1628

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1629

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1630

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1635

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1637

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1642

tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1647

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1654

tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1656

tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1661

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1667

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1670

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1672

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1678

tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1682

tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1686

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1687

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1688

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1689

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1690

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1691

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1719

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1721

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1725

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1730

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1851

u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1894

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1895

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1899

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1900

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1902

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1908

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1909

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1911

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1917

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1918

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1920

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1925

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1926

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1928

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1934

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1935

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1937

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1943

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1944

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1946

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1954

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1955

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1957

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1965

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1966

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1967

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1968

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1970

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1989

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1990

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1992

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1994

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1995

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1996

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1998

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2001

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2005

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2014

tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2036

tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2038

tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2096

tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2098

tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2114

tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2115

tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2119

tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2123

tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2127

tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2128

tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2156

tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2157

tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2158

tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2162

tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2163

tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2167

tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2168

tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2172

tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2173

tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2182

tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2282

cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2284

cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2295

tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2311

tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2312

tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

243

tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3020

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3026

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3049

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3055

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3079

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3084

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

314

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

316

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3229

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3244

tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3259

tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

350

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

356

tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

360

tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

363

tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

399

tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

451

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

453

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

459

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

461

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

496

tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

537

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

538

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

539

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

540

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

542

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

543

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

549

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

550

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

551

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

552

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

553

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

555

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

556

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

562

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

563

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

564

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

565

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

566

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

568

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

569

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

629

tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

633

tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1192

REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1227

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1229

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1232

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1234

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1277

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1279

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1283

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1286

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1290

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1293

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1471

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1472

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1473

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1488

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1489

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1494

tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1497

tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1501

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1504

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1508

tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1511

tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1553

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1573

tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1576

tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1579

tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1601

tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1605

tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1609

tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1613

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1614

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1615

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1616

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1617

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1618

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1622

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1626

tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1627

tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1631

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1632

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1645

tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1659

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1660

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1661

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1662

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1666

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1670

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1674

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1675

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1676

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1677

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1681

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1696

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1700

tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1704

tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1705

tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1706

tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1707

tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

402

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

404

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

410

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

412

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

454

tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3848

tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3850

tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3852

tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5062

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5065

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5069

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5072

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5075

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5078

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5186

data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5188

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5361

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5363

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5433

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5435

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5437

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5439

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5472

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5890

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5927

tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5964

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6001

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6077

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6078

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6079

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6137

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6158

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6159

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6160

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6161

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6215

tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6236

tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6237

tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6238

tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6239

tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6292

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6313

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6314

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6315

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6316

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6449

tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6462

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6464

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6467

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6481

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6489

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6519

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6520

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6522

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6562

tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6563

tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6667

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6688

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6689

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6690

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6758

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6780

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6781

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6782

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6787

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6795

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6817

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6818

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6820

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6827

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6829

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6832

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6927

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6936

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6938

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6940

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6942

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6945

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6963

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6973

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6975

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6978

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6980

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6981

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6983

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6984

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7005

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7010

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7622

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7625

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7631

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7647

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7654

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9078

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9084

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9131

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9137

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9245

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9259

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9291

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9305

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9336

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9430

tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9435

tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9440

tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9445

tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9538

tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9540

tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9542

tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1958

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1961

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1965

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1968

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1971

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1974

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2076

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2154

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2156

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2225

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2227

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2229

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2231

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2256

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2372

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2373

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2402

tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2421

tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2500

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2521

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2522

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2523

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2524

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2544

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2565

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2566

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2567

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2568

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2588

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2610

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2611

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2612

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2640

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2641

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2642

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2665

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2696

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2699

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2705

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2708

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2721

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2722

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2727

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2762

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2763

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2764

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2787

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2819

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2822

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2828

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2831

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2844

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2845

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2850

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2880

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2881

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2882

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2886

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2887

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2913

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2932

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2979

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2980

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2984

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2985

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3001

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3002

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3006

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3007

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3023

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3024

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3025

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3026

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3030

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3031

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3032

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3033

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3123

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3124

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3251

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3252

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3253

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3276

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3307

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3310

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3316

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3319

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3332

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3333

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3338

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3469

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3470

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3471

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3494

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3526

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3529

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3535

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3538

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3551

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3552

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3557

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3688

tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3700

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3702

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3705

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3710

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3738

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3739

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3778

tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3779

tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3824

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3826

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3828

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3830

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3832

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3834

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3836

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3838

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3840

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3842

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3849

data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3851

data = REG_SET_FIELD(data, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3854

data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3855

data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3974

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3975

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3976

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3980

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3981

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4007

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4026

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4087

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4109

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4110

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4111

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4116

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4124

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4146

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4147

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4149

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4152

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4154

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4160

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4162

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4165

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4254

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4263

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4265

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4267

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4269

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4272

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4290

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4300

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4302

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4304

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4305

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4308

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4309

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4312

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4330

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4333

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4335

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4337

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4350

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4355

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4684

tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4688

tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4976

tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4977

tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4985

tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5011

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5012

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5013

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5014

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5078

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5080

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5082

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5084

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5086

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5091

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5093

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5095

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5097

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5099

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5104

tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5121

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5122

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5123

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5124

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5511

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5512

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5513

data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5514

data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5518

data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5524

data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6356

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6358

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6364

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6366

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6413

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6415

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6421

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6423

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6532

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6546

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6578

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6592

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6623

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6728

tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6733

tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6738

tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6743

tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6802

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6804

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6806

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6808

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6812

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6814

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6816

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6818

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6899

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6901

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6905

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6907

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6911

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6913

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6917

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6919

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6933

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6935

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6939

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6941

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6945

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6947

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6951

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6953

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6963

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6965

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6969

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6971

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6975

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6977

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6981

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6983

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1340

data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1341

data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1667

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1670

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1674

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1677

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1680

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1683

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1784

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1821

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1823

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1885

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1887

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1889

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1891

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1916

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2032

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2033

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2130

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2131

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2135

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2136

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2152

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2153

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2157

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2158

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2174

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2175

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2176

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2177

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2181

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2182

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2183

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2184

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2210

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2213

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2219

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2222

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2252

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2255

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2261

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2264

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2331

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2332

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2410

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2411

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2412

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2435

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2464

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2465

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2470

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2554

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2555

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2556

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2579

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2609

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2610

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2615

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2679

tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2691

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2693

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2696

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2701

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2729

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2730

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2777

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2779

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2781

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2783

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2785

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2787

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2789

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2791

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2793

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2795

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2864

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2865

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2866

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2870

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2871

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2895

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2914

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2981

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2982

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2983

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2988

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2994

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2999

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3021

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3022

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3024

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3027

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3029

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3035

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3037

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3040

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3127

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3136

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3138

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3140

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3142

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3145

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3163

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3173

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3175

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3177

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3178

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3180

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3181

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3184

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3202

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3205

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3207

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3209

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3222

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3227

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4108

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4109

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4110

data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4111

data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4115

data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4121

data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4717

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4719

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4725

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4727

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4768

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4770

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4776

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4778

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4887

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4901

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4933

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4947

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4978

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5254

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5256

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5258

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5260

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5264

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5266

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5268

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5270

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5349

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5351

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5355

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5357

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5361

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5363

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5367

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5369

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5382

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5384

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5388

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5390

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1310

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1312

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1630

tcp_addr_config = REG_SET_FIELD(RREG32(mmTCP_ADDR_CONFIG),

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1565

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1567

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1923

sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1925

sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1927

sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1929

sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1931

sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1933

sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1935

sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2012

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2013

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2014

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2015

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2954

tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4005

value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4006

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4007

value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4008

value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1546

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1572

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1598

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1618

tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1619

tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1623

tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1832

gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1835

gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1838

gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3394

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3396

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3399

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3401

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3404

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3406

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3739

sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3741

sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3743

sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3752

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3753

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3754

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3759

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3760

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3761

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3795

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3796

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3797

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3798

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3848

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3849

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3850

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3851

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3992

data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3993

data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3994

data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3995

data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4089

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4090

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4091

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4093

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4094

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4095

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4203

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4205

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4207

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4210

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4218

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4243

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4244

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4245

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4246

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4248

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4423

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4429

tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4442

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4452

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4454

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4457

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4459

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4460

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4461

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4462

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4480

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4483

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4485

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4487

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4502

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4507

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4508

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4512

tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4516

tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4905

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4907

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4909

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4916

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4922

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4924

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4926

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4928

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4935

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4938

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5008

tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5009

tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5044

tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5045

tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6352

value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6353

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6354

value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6355

value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1731

data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1732

data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1733

data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1750

data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1751

data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1780

data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1781

data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1782

data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1799

data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1800

data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2504

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2506

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2509

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2511

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2514

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2516

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2573

data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2575

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2648

tmp = REG_SET_FIELD(tmp, SQ_CONFIG, DISABLE_BARRIER_WAITCNT,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2684

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2686

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2691

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2693

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2696

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2698

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2759

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2760

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2761

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2763

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3000

data = REG_SET_FIELD(data, RLC_PG_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3014

data = REG_SET_FIELD(data, RLC_PG_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3028

data = REG_SET_FIELD(data, RLC_PG_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3041

data = REG_SET_FIELD(data, RLC_PG_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3054

data = REG_SET_FIELD(data, RLC_PG_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3071

data = REG_SET_FIELD(data, RLC_PG_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3084

data = REG_SET_FIELD(data, RLC_PG_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3245

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3246

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3247

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3248

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3249

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3250

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3251

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3252

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3253

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3254

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3255

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3256

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3404

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3405

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3407

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3434

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3436

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3439

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3443

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3496

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3497

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3577

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3586

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3588

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3590

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3592

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3595

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3614

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3624

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3626

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3629

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3631

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3632

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3633

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3634

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3656

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3661

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4002

tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4004

tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4006

tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4148

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4150

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4155

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4162

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4709

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4737

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4765

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5922

value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5923

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5924

value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5925

value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5984

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5990

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6045

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6081

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

101

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

105

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

108

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

111

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

114

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

98

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1425

REG_SET_FIELD(0, VML2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1431

REG_SET_FIELD(0, VML2_WALKER_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1437

REG_SET_FIELD(0, UTCL2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1443

REG_SET_FIELD(0, ATC_L2_CACHE_2M_DSM_CNTL, WRITE_COUNTERS, 1) },

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1449

REG_SET_FIELD(0, ATC_L2_CACHE_32K_DSM_CNTL, WRITE_COUNTERS, 1) },

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1455

REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) },

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1698

value = REG_SET_FIELD(value, GCEA_ERR_STATUS, CLEAR_ERROR_STATUS, 0x1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1736

reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1794

data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1804

data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

409

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

758

data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

775

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

776

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

777

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

796

tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

800

tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

805

tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

865

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

868

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

872

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

875

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

878

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

881

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1244

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1292

data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1309

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1311

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1318

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1320

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1324

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1327

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1514

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1515

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1516

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1773

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1774

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1853

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1862

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1864

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1866

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1868

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1871

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1874

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1893

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1903

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1905

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1908

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1910

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1911

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1912

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1913

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1935

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1940

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2443

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2445

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2450

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2457

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3056

value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3057

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3058

value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3059

value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3103

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3109

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3166

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3206

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3524

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3528

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3532

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3536

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3544

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3547

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4521

data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4530

data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4962

tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4963

tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

695

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

698

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

702

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

705

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

708

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

711

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

813

tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

815

tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

194

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

195

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

196

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

198

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

200

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

201

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

219

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

220

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

221

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

224

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

226

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

227

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

228

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

232

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

233

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

238

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

239

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

242

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

243

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

249

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

250

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

254

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

263

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

264

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

265

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

301

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

302

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

304

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

308

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

310

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

312

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

314

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

316

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

318

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

322

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

396

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

397

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

419

tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

429

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

431

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

433

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

435

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

437

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

440

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

442

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

444

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

446

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

448

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

450

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

453

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

455

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

65

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

70

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

71

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

72

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

73

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

199

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

200

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

201

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

203

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

205

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

206

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

224

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

225

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

226

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

231

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

232

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

233

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

237

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

238

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

243

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

244

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

247

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

248

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

254

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

255

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

259

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

268

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

269

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

270

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

307

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

309

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

311

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

313

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

315

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

317

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

319

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

321

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

323

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

327

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

401

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

402

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

424

tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

434

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

436

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

438

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

440

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

442

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

445

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

447

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

449

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

451

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

453

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

455

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

458

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

460

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

70

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

71

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

72

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

73

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

74

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

75

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

161

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

162

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

163

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

165

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

167

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

169

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

180

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

181

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

183

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

185

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

186

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

187

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

191

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

192

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

197

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

198

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

201

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

202

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

209

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

210

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

212

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

213

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

223

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

224

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

226

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

228

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

266

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

267

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

269

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

271

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

274

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

276

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

278

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

280

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

282

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

284

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

291

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

358

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

359

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

382

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

384

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

386

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

388

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

390

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

394

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

396

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

398

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

400

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

402

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

404

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

407

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

409

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

177

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

206

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

208

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

210

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

212

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

214

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

216

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

231

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

232

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

234

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

236

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

237

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

238

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

242

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

243

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

248

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

249

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

252

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

253

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

261

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

262

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

264

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

265

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

279

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

280

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

282

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

284

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

348

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

349

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

351

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

353

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

356

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

358

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

360

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

362

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

364

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

366

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

374

tmp = REG_SET_FIELD(

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

461

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

462

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

471

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

495

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

497

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

499

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

501

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

503

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

507

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

509

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

511

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

513

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

515

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

517

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

520

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

522

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

193

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

194

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

195

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

197

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

199

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

215

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

216

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

217

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

220

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

222

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

223

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

224

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

228

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

234

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

235

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

238

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

239

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

245

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

246

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

250

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

259

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

260

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

261

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

291

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

292

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

294

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

296

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

298

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

300

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

302

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

304

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

308

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

312

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

374

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

375

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

398

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

400

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

402

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

404

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

406

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

409

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

411

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

413

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

415

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

417

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

419

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

422

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

424

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

61

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

63

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

64

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

65

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

66

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

197

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

198

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

199

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

201

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

203

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

221

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

222

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

223

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

226

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

228

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

230

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

234

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

235

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

240

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

241

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

244

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

245

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

251

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

252

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

256

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

265

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

266

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

267

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

303

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

304

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

308

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

310

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

312

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

314

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

316

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

318

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

320

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

324

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

398

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

399

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

429

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

431

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

433

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

435

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

437

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

440

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

442

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

444

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

446

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

448

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

450

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

453

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

455

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

64

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

66

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

70

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

71

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

72

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

191

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

192

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

193

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

195

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

197

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

198

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

216

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

217

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

218

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

221

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

223

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

224

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

225

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

230

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

235

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

236

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

239

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

240

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

246

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

247

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

251

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

260

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

261

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

262

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

298

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

299

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

301

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

303

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

305

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

307

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

309

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

311

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

313

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

315

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

319

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

393

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

394

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

416

tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

426

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

428

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

430

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

432

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

434

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

437

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

439

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

441

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

443

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

445

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

447

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

450

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

452

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

60

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

62

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

63

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

64

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

65

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

66

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

196

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

197

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

198

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

200

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

202

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

203

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

221

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

222

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

223

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

226

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

228

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

230

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

234

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

235

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

240

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

241

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

244

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

245

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

251

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

252

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

256

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

265

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

266

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

267

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

303

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

304

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

308

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

310

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

312

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

314

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

316

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

318

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

320

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

324

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

386

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

387

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

414

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

416

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

418

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

420

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

422

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

425

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

427

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

429

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

431

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

433

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

435

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

438

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

440

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

63

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

65

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

66

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

70

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

71

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1001

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

400

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

402

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

404

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

406

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

408

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

410

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

431

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

434

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

437

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

440

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

710

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

711

data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

712

data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

713

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

715

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

716

data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

717

data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

718

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

733

data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

735

data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

749

data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

751

data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

80

blackout = REG_SET_FIELD(blackout,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

95

tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

98

tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

99

tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

995

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

104

blackout = REG_SET_FIELD(blackout,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

118

tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1180

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1186

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

121

tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

122

tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

284

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

289

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

308

tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

528

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

530

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

532

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

534

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

536

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

538

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

559

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

561

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

563

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

565

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

567

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

569

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

571

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

627

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

628

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

629

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

630

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

631

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

635

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

636

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

637

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

638

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

639

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

640

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

641

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

643

tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

644

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

649

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

650

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

651

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

661

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

662

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

663

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

691

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

692

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

693

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

747

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

748

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

749

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

753

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

868

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

869

data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

870

data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

871

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

873

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

874

data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

875

data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

876

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

891

data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

893

data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

907

data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

909

data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1311

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1317

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

186

blackout = REG_SET_FIELD(blackout,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

200

tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

203

tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

204

tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

459

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

464

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

494

tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

743

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

745

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

747

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

749

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

751

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

753

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

755

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

776

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

778

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

780

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

782

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

784

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

786

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

788

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

844

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

845

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

846

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

847

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

848

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

852

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

853

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

854

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

855

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

856

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

857

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

858

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

861

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

862

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

867

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

868

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

869

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

873

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

874

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

875

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

876

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

877

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

878

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

879

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

880

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

881

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

882

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

883

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

884

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

894

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

895

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

896

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

924

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

925

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

926

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

927

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

928

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

929

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

930

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

931

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

932

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

933

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

981

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

982

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

983

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

987

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

776

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

778

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

779

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

780

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

781

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

782

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

783

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

784

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

102

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

107

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

111

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

120

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

122

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

129

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

131

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

58

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

60

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

66

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

68

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

70

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

72

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

74

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

76

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

78

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

80

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

88

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

91

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

95

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

98

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

101

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

105

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

108

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

112

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

115

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

123

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

125

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

132

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

134

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

69

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

71

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

76

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

78

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

80

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

82

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

84

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

86

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

88

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

90

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

98

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

108

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

110

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

117

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

52

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

60

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

62

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

64

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

66

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

68

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

70

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

72

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

74

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

82

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

85

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

89

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

92

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

96

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

99

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

101

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

108

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

46

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

51

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

53

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

55

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

57

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

59

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

61

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

63

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

65

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

73

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

76

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

80

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

83

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

87

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

90

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

99

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

121

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

123

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

130

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

131

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

132

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

135

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

149

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

152

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

206

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

215

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

221

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

372

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

65

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

66

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

84

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

85

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

101

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

103

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

105

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

143

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

152

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

163

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

168

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

219

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

221

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

223

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

225

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

229

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

231

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

232

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

233

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

243

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

246

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

250

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

280

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

282

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

283

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

340

ih_chicken = REG_SET_FIELD(ih_chicken,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

360

tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

365

tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

374

tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

381

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

385

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

386

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

387

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

451

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

466

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

472

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

684

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

686

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

688

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

690

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

692

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

716

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

723

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

725

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

727

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

730

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

732

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

734

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

737

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

741

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

743

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

745

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

748

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

750

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

752

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

755

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

101

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

103

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

105

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

191

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

193

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

195

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

197

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

201

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

203

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

204

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

205

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

215

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

218

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

222

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

252

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

254

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

255

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

312

ih_chicken = REG_SET_FIELD(ih_chicken,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

331

tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

336

tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

345

tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

352

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

356

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

357

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

358

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

421

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

434

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

440

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

659

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

661

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

663

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

665

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

667

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

693

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

700

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

702

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

704

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

707

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

709

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

711

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

714

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

718

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

720

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

722

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

725

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

727

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

729

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

732

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

101

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

103

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

105

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

191

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

193

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

195

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

197

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

201

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

203

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

204

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

205

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

215

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

218

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

222

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

252

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

254

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

255

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

312

ih_chicken = REG_SET_FIELD(ih_chicken,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

331

tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

336

tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

345

tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

352

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

356

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

357

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

358

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

421

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

434

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

440

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

649

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

651

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

653

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

655

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

657

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

683

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

690

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

692

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

694

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

697

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

699

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

701

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

704

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

708

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

710

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

712

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

715

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

717

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

719

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

722

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

110

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

113

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

56

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

57

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

58

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

59

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

60

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

61

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

62

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

88

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

89

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

90

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

91

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

92

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

93

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

94

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

110

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

113

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

56

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

57

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

58

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

59

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

60

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

61

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

62

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

88

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

89

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

90

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

91

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

92

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

93

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

94

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1001

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1063

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1064

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1069

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1124

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1143

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1164

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1166

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1168

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1169

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1170

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1171

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1172

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1178

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1180

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1182

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1184

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1187

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1196

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1219

data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1224

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1234

data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1526

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1528

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

406

value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

408

value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

410

value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

960

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

961

data = REG_SET_FIELD(data, CP_MES_CNTL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

983

data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

984

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

994

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

995

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

996

data = REG_SET_FIELD(data, CP_MES_CNTL,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

998

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

999

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1110

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1112

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1122

data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1124

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1141

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1142

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1143

data = REG_SET_FIELD(data, CP_MES_CNTL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1145

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1146

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1147

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1225

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1226

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1231

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1284

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1303

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1324

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1326

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1328

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1329

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1330

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1331

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1332

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1338

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1340

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1342

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1344

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1347

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1357

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1386

data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1391

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1401

data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1706

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1708

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

387

tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

388

tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

396

tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

431

value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

433

value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

435

value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

132

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

144

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

145

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

146

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

148

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

150

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

152

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

166

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

167

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

169

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

171

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

172

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

173

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

177

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

178

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

183

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

184

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

187

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

188

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

194

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

195

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

204

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

205

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

206

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

294

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

295

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

297

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

299

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

302

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

304

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

306

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

308

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

310

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

312

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

316

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

403

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

404

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

413

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

433

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

435

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

437

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

439

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

441

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

445

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

447

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

449

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

451

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

453

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

455

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

458

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

460

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1342

reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

150

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

162

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

163

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

164

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

166

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

168

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

170

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

208

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

209

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

211

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

213

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

214

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

215

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

219

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

220

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

225

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

226

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

229

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

230

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

237

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

239

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

242

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

244

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

255

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

256

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

258

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

260

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

302

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

303

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

305

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

307

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

310

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

312

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

314

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

316

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

318

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

320

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

326

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

387

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

388

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

397

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

417

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

419

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

421

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

423

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

425

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

429

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

431

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

433

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

435

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

437

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

439

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

442

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

444

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

187

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

201

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

203

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

205

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

207

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

209

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

211

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

219

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

221

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

223

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

225

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

227

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

229

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

277

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

278

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

281

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

283

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

285

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

287

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

292

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

294

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

299

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

300

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

303

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

304

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

312

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

314

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

317

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

319

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

334

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

335

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

337

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

340

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

397

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

399

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

401

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

403

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

405

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

407

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

409

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

411

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

413

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

415

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

422

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

487

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

488

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

495

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

497

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

520

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

547

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

549

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

551

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

553

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

555

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

558

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

560

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

562

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

564

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

566

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

568

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

571

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

573

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

125

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

127

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

128

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

129

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

130

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

131

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

132

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

133

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

253

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

265

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

266

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

267

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

269

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

271

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

289

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

290

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

291

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

294

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

296

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

297

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

298

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

302

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

303

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

308

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

309

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

312

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

313

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

319

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

320

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

324

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

333

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

334

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

335

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

374

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

375

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

377

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

379

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

382

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

384

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

386

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

388

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

390

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

392

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

396

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

458

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

459

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

465

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

487

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

489

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

491

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

493

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

495

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

498

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

500

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

502

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

504

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

506

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

508

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

511

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

513

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

181

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

193

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

194

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

195

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

197

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

199

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

211

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

212

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

213

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

216

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

218

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

219

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

220

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

224

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

225

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

230

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

231

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

234

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

235

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

241

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

242

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

246

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

255

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

256

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

257

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

290

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

291

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

293

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

295

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

298

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

300

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

302

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

304

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

306

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

308

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

312

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

388

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

389

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

395

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

412

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

414

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

416

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

418

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

420

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

423

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

425

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

427

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

429

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

431

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

433

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

436

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

438

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

64

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

66

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

67

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

68

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

69

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

70

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

71

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

72

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

206

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

218

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

219

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

220

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

222

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

224

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

225

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

243

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

244

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

245

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

248

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

250

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

251

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

252

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

256

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

257

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

262

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

263

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

266

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

267

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

273

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

274

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

278

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

287

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

288

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

289

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

328

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

329

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

331

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

333

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

336

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

338

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

340

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

342

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

344

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

346

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

350

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

412

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

413

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

419

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

441

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

443

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

445

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

447

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

449

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

452

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

454

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

456

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

458

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

460

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

462

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

465

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

467

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

81

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

83

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

84

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

85

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

86

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

87

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

88

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

89

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

212

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

224

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

225

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

226

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

228

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

230

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

231

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

243

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

244

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

245

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

248

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

250

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

251

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

252

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

256

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

257

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

262

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

263

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

266

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

267

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

273

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

274

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

278

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

287

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

288

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

289

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

322

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

323

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

325

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

327

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

330

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

332

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

334

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

336

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

338

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

340

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

344

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

406

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

407

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

413

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

430

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

432

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

434

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

436

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

438

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

441

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

443

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

445

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

447

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

449

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

451

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

454

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

456

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

88

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

90

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

91

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

92

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

93

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

94

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

95

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

96

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

198

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

210

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

211

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

212

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

214

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

216

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

217

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

235

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

236

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

237

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

240

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

242

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

243

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

244

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

248

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

249

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

254

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

255

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

258

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

259

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

265

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

266

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

270

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

279

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

280

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

281

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

320

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

321

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

323

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

325

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

328

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

330

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

332

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

334

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

336

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

338

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

342

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

404

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

405

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

411

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

433

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

435

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

437

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

439

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

441

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

444

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

446

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

448

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

450

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

452

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

454

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

457

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

459

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

81

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

83

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

84

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

85

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

86

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

87

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

88

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

89

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

172

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

174

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type ? : 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

175

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

176

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

177

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

178

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

179

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

180

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

304

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

316

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

317

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

318

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

320

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

322

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

323

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

335

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

336

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

337

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

340

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

342

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

343

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

344

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

348

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

349

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

354

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

355

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

358

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

359

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

365

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

366

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

370

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

379

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

380

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

381

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

415

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

416

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

418

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

420

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

423

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

425

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

427

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

429

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

431

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

433

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

437

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

492

tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

493

tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

502

tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

503

tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

548

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

549

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

555

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

572

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

574

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

576

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

578

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

580

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

583

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

585

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

587

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

589

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

591

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

593

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

596

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

598

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

199

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

211

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

212

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

213

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

215

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

217

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

218

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

236

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

237

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

238

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

241

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

243

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

244

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

245

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

249

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

250

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

255

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

256

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

259

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

260

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

266

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

267

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

271

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

280

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

281

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

282

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

321

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

322

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

324

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

326

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

329

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

331

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

333

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

335

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

337

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

339

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

343

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

405

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

406

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

412

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

435

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

437

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

439

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

441

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

443

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

446

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

448

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

450

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

452

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

454

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

456

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

459

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

461

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

73

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

76

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

77

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

78

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

79

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

80

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

81

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

82

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

166

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

184

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

186

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

188

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

190

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

192

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

194

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

238

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

240

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

243

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

245

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

247

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

249

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

256

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

258

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

265

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

266

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

269

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

270

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

277

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

279

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

292

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

293

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

294

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

342

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

344

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

347

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

349

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

352

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

354

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

356

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

358

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

360

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

362

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

366

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

454

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

456

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

466

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

490

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

493

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

496

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

499

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

502

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

506

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

509

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

512

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

515

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

518

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

521

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

525

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

528

tmp = REG_SET_FIELD(tmp,

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

142

reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

245

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

333

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

326

reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

348

reg = REG_SET_FIELD(reg, MAILBOX_CONTROL,

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

359

reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

506

tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN,

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

539

tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

116

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

118

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

120

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

131

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

162

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

163

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

166

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

217

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

219

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

221

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

223

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

227

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

229

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

230

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

231

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

241

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

244

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

248

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

278

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

280

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

338

ih_chicken = REG_SET_FIELD(ih_chicken,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

344

ih_chicken = REG_SET_FIELD(ih_chicken,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

430

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

442

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

448

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

654

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

656

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

658

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

660

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

662

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

117

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

121

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

125

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

129

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

133

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

138

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

169

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

171

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

173

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

191

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

195

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

199

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

203

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

207

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

212

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

232

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

236

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

490

bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

524

bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

75

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

79

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

83

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

87

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

91

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

96

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

120

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

123

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

127

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

143

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

146

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

149

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

168

tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

170

REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

172

REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

192

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

195

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

199

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

218

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

222

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

336

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

337

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

113

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

117

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

121

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

125

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

129

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

134

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

164

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

166

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

168

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

187

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

191

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

195

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

199

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

203

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

208

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

228

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

232

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

570

bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

604

bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

72

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

76

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

80

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

84

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

88

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

93

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

100

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

118

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

119

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

120

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

138

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

139

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

142

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

157

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

159

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

267

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

268

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

274

data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

97

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

98

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

122

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

123

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

125

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

232

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

234

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

76

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

77

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

79

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

92

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

95

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

98

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

100

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

104

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

123

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

126

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

129

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

143

reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

155

tmp = REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

157

REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

159

REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

180

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

183

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

187

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

209

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

213

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

269

data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

271

data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

72

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

75

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

79

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

97

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

115

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

118

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

122

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

137

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

140

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

143

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

156

reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

168

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

170

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

172

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

194

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

197

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

201

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

223

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

227

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

376

data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

378

data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

386

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

388

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

171

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

172

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

174

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

196

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

199

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

202

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

220

tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

221

REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

222

REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

239

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

240

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 8);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

242

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

300

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

302

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

377

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

434

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

467

bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

512

bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

636

int_eoi = REG_SET_FIELD(int_eoi,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

100

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

113

reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

125

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

127

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

129

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

152

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

155

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

159

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

181

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

185

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

241

data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

243

data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

72

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

75

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

79

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

94

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

97

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

103

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

106

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

109

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

120

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

123

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

126

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

137

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

140

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

143

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

154

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

157

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

160

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

183

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

187

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

192

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

197

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

200

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

203

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

206

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

209

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

218

doorbell_range = REG_SET_FIELD(doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

221

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

247

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

249

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

251

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

269

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

273

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

278

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

281

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

284

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

287

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

290

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

294

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

297

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

333

REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

336

REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

531

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

577

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

86

REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

89

REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

92

REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

95

REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,

sys/dev/pci/drm/amd/amdgpu/nv.c

321

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/nv.c

322

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);

sys/dev/pci/drm/amd/amdgpu/nv.c

323

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/amdgpu/nv.c

324

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

161

tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

162

tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

163

tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

174

tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

175

tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1001

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1012

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1017

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

280

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

282

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

345

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

348

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

386

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

388

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

429

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

431

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

432

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

449

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

458

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

462

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

464

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

952

tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

959

tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

996

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1334

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1339

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1350

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1355

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

456

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

458

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

521

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

524

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

581

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

583

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

592

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

594

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

623

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

625

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

669

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

671

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

672

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

690

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

698

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

700

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

702

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

717

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

721

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

728

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

732

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

734

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1012

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1058

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1071

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1073

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1074

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1113

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1127

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1129

doorbell_offset = REG_SET_FIELD(doorbell_offset,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1147

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1153

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1157

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1159

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1198

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1212

doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1214

doorbell_offset = REG_SET_FIELD(doorbell_offset,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1233

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1239

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1243

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1245

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1415

temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1421

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2067

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2157

sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

606

temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

929

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

932

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

963

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

967

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1003

temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1008

temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1015

temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

170

val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

171

val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1754

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

176

val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

178

val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1853

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

503

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

506

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

509

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

516

doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

517

doorbell_offset = REG_SET_FIELD(doorbell_offset,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

556

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

560

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

607

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

653

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

667

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

669

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

670

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

708

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

744

doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

746

doorbell_offset = REG_SET_FIELD(doorbell_offset,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

764

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

770

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

774

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

776

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

835

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

850

doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

852

doorbell_offset = REG_SET_FIELD(doorbell_offset,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

871

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

877

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

881

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

883

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1335

grbm_soft_reset = REG_SET_FIELD(0,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1575

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1596

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1600

cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1617

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1686

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

570

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

573

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

630

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

673

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

707

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

709

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

710

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

735

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

747

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

772

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

773

doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

776

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

794

temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

797

temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

802

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

803

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

817

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

822

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

826

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

828

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

992

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1483

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1505

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1509

cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1527

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1592

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

420

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

423

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

489

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

520

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

556

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

558

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

559

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

585

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

597

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

617

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

618

doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

621

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

641

temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

644

temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

649

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

650

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

664

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

669

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

673

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

675

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

771

grbm_soft_reset = REG_SET_FIELD(0,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

892

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1602

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

401

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

404

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

437

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

467

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

499

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

501

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

502

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

505

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

533

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

534

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

535

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

555

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

556

doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

559

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

578

temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

584

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

585

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

600

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

601

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

606

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

610

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

612

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

885

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1536

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

405

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

408

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

460

mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

491

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

493

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

494

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

497

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

525

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

527

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

529

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

531

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

551

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

552

doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

555

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

574

temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

580

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

581

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

595

temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

596

temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, RESET, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

601

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

605

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

607

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

719

tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

728

tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

905

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/si.c

1610

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);

sys/dev/pci/drm/amd/amdgpu/si.c

1611

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

119

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

120

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

121

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

122

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

128

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

130

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

310

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

318

reg = REG_SET_FIELD(reg,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

323

reg = REG_SET_FIELD(reg,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

328

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

389

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

391

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

397

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

401

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

448

reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

452

reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

53

reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/soc15.c

367

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/soc15.c

368

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);

sys/dev/pci/drm/amd/amdgpu/soc15.c

369

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/amdgpu/soc15.c

370

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

sys/dev/pci/drm/amd/amdgpu/soc15.c

772

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);

sys/dev/pci/drm/amd/amdgpu/soc15.c

773

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);

sys/dev/pci/drm/amd/amdgpu/soc15.c

819

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,

sys/dev/pci/drm/amd/amdgpu/soc15.c

821

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,

sys/dev/pci/drm/amd/amdgpu/soc21.c

242

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/soc21.c

243

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);

sys/dev/pci/drm/amd/amdgpu/soc21.c

244

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/amdgpu/soc21.c

245

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

sys/dev/pci/drm/amd/amdgpu/soc24.c

105

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/soc24.c

106

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);

sys/dev/pci/drm/amd/amdgpu/soc24.c

107

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/amdgpu/soc24.c

108

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

117

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

119

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

126

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

127

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

129

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

130

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

133

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

147

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

149

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

152

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

208

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

219

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

225

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

390

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

64

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

65

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

81

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

82

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

408

odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

121

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

134

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

198

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

208

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

413

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

416

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

423

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

52

rsmu_umc_val = REG_SET_FIELD(rsmu_umc_val,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

67

rsmu_umc_val = REG_SET_FIELD(rsmu_umc_val,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

282

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

292

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

380

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

393

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

311

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

136

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_GeccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

194

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

207

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

253

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

263

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

403

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

406

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

413

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

130

data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, IC_FORCE_GPUVM, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

131

data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, DC_FORCE_GPUVM, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

135

data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

136

data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

140

data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

155

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

156

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

157

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

158

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

190

data = REG_SET_FIELD(data, VCN_AGDB_CTRL0, OFFSET,

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

192

data = REG_SET_FIELD(data, VCN_AGDB_CTRL0, EN, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

196

data = REG_SET_FIELD(data, VCN_AGDB_CTRL1, OFFSET,

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

198

data = REG_SET_FIELD(data, VCN_AGDB_CTRL1, EN, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

202

data = REG_SET_FIELD(data, VCN_AGDB_CTRL2, OFFSET,

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

204

data = REG_SET_FIELD(data, VCN_AGDB_CTRL2, EN, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

208

data = REG_SET_FIELD(data, VCN_AGDB_CTRL3, OFFSET,

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

210

data = REG_SET_FIELD(data, VCN_AGDB_CTRL3, EN, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

221

data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, OFFSET, ring->doorbell_index);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

222

data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

251

data = REG_SET_FIELD(data, VCN_RB_ENABLE, UMSCH_RB_EN, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

255

data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

73

data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

77

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

78

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

79

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

80

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

84

data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

85

data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, EXE_DISABLE, 0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

86

data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, CACHE_POLICY, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

421

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

422

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

423

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

424

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

425

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

426

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1177

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

839

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

840

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

841

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

842

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

843

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

844

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1086

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1087

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1088

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1089

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1090

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1091

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

919

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

920

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

650

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

651

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

655

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

656

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1134

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1135

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1136

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1137

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1138

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

970

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

971

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

972

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

973

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

974

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1132

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1133

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1134

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1135

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1136

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2078

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2079

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2080

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2081

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2082

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

953

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

954

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

955

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

956

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

957

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1114

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1115

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1116

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1117

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1118

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1304

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1305

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1306

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1307

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1308

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1527

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1528

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1529

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1530

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1531

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1139

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1140

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1141

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1142

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1143

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1330

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1331

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1332

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1333

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1334

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1520

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1521

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1522

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1523

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1524

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

106

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

107

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

110

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

162

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

164

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

166

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

168

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

172

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

174

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

175

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

176

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

186

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

189

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

193

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

223

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

225

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

278

ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

360

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

372

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

378

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

589

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

592

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

594

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

596

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

598

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

600

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

114

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

115

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

121

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

130

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

141

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

146

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

198

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

200

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

202

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

204

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

208

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

210

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

211

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

212

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

222

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

225

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

229

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

259

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

261

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

290

val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

291

val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

326

ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

340

ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

442

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

456

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

462

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

685

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

687

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

689

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

691

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

693

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

695

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

697

data = REG_SET_FIELD(data, IH_CLK_CTRL,

sys/dev/pci/drm/amd/amdgpu/vi.c

1289

tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vi.c

1291

tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);

sys/dev/pci/drm/amd/amdgpu/vi.c

1367

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);

sys/dev/pci/drm/amd/amdgpu/vi.c

1368

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);

sys/dev/pci/drm/amd/amdgpu/vi.c

582

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/vi.c

583

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);

sys/dev/pci/drm/amd/amdgpu/vi.c

584

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/amdgpu/vi.c

585

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

110

vpe_colla_cntl = REG_SET_FIELD(vpe_colla_cntl, VPEC_COLLABORATE_CNTL,

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

115

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, MASTER_ID, 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

116

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, MASTER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

117

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, SLAVE0_ID, 1);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

118

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, SLAVE0_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

140

ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

163

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

164

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

219

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

220

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_PRIV, 1);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

221

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_VMID, 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

236

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

251

doorbell_offset = REG_SET_FIELD(doorbell_offset, VPEC_QUEUE0_DOORBELL_OFFSET, OFFSET, ring->doorbell_index + i*4);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

255

doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

260

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

261

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

265

ib_cntl = REG_SET_FIELD(ib_cntl, VPEC_QUEUE0_IB_CNTL, IB_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

288

queue_reset = REG_SET_FIELD(queue_reset, VPEC_QUEUE_RESET_REQ, QUEUE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

322

vpe_cntl = REG_SET_FIELD(vpe_cntl, VPEC_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

80

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

81

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, halt ? 1 : 0);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

842

data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

843

data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

849

data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

850

data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

856

data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

857

data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

863

data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

864

data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

870

data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

871

data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

141

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

144

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

161

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

165

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

274

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

322

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

391

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

392

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

393

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

394

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

415

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

421

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

191

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

192

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

193

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

194

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

163

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

206

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

95

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

98

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1180

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1183

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1253

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1275

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1166

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1169

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1194

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1223

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1347

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1348

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1355

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1367

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1368

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1369

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1370

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1371

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1372

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1383

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1384

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1388

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1443

data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1089

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1092

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1120

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1171

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1202

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1203

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1210

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1222

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1223

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1224

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1225

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1226

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1227

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1238

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1239

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1243

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1305

data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1343

data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1356

data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1882

data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1932

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1939

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1940

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1944

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1011

data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

878

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

879

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

887

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

891

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

903

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

904

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

905

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

906

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

907

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

908

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

920

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

921

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

925

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

929

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

930

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

934

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

983

data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

998

data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,