Symbol: REG_GET_FIELD
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
100
*trap_mask_prev = REG_GET_FIELD(kfd_dbg_trap_cntl_prev, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
329
2 << REG_GET_FIELD(m->cp_hqd_pq_control,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
424
uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
426
if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
429
if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
518
bool is_active = !!REG_GET_FIELD(status, SDMA_RLC0_CONTEXT_STATUS, SELECTED);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
254
2 << REG_GET_FIELD(m->cp_hqd_pq_control,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
563
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
567
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
568
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
575
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
842
*trap_mask_prev = REG_GET_FIELD(data, SPI_GDBG_TRAP_MASK, EXCP_EN);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
240
2 << REG_GET_FIELD(m->cp_hqd_pq_control,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
225
2 << REG_GET_FIELD(m->cp_hqd_pq_control,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
696
uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
698
if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
701
if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
263
uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
265
if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
268
if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
398
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
402
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
403
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
410
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
561
return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
433
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
437
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
438
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
445
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
268
2 << REG_GET_FIELD(m->cp_hqd_pq_control,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
776
*trap_mask_prev = REG_GET_FIELD(data, SPI_GDBG_TRAP_MASK, EXCP_EN);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
46
if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
47
REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
57
if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
58
(REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
59
REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
60
REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
61
REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
62
REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5048
!REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5051
*memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5072
!REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5077
*err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
sys/dev/pci/drm/amd/amdgpu/cik.c
1923
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/cik.c
1924
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/cik.c
1941
if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
197
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
203
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
349
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
364
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
421
if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
491
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
638
if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
672
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1159
if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
449
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
228
adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
231
adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
234
adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
652
v0 = REG_GET_FIELD(hw_assert_msklo,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
654
v1 = REG_GET_FIELD(hw_assert_msklo,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
656
v28 = REG_GET_FIELD(hw_assert_mskhi,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
658
v31 = REG_GET_FIELD(hw_assert_mskhi,
sys/dev/pci/drm/amd/amdgpu/df_v4_3.c
39
v0 = REG_GET_FIELD(hw_assert_msklo,
sys/dev/pci/drm/amd/amdgpu/df_v4_3.c
41
v1 = REG_GET_FIELD(hw_assert_msklo,
sys/dev/pci/drm/amd/amdgpu/df_v4_3.c
43
v28 = REG_GET_FIELD(hw_assert_mskhi,
sys/dev/pci/drm/amd/amdgpu/df_v4_3.c
45
v31 = REG_GET_FIELD(hw_assert_mskhi,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4610
1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4629
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4636
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4639
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4642
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4645
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5335
REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5336
(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5896
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5933
if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5970
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6007
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6039
(REG_GET_FIELD(bootload_status,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6143
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6221
if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6298
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6673
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7584
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7602
if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7646
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7653
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7860
return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7884
if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7895
if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1984
gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1988
gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2003
gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2007
gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2124
REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2125
(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2144
REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2506
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2550
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2595
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2652
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2670
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2732
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2774
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2793
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2855
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2919
if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2938
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3061
(REG_GET_FIELD(bootload_status,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3263
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3281
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3343
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3481
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3500
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3562
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4013
if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4032
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4705
1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4710
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4717
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4720
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4723
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4726
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4944
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4962
if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5317
return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5332
if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c
53
if (REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA0_FED_ERR) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c
54
REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA1_FED_ERR))
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c
93
if (REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA0_FED_ERR) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c
94
REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA1_FED_ERR)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1693
gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1697
gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1712
gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1716
gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2303
(REG_GET_FIELD(bootload_status,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2422
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2440
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2475
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2566
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2585
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2620
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2901
if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2920
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3545
1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3550
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3557
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3560
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3563
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3566
REG_GET_FIELD(adev->gfx.config.gb_addr_config,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3797
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3815
if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3909
return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3925
if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1336
data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1542
return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1604
(REG_GET_FIELD(RREG32(mmCGTS_TCC_DISABLE),
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1606
REG_GET_FIELD(RREG32(mmCGTS_USER_TCC_DISABLE),
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4216
adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4218
adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4226
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4227
dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4230
dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4231
dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1784
adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1786
adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1794
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1795
dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1798
dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1799
dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1818
tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3424
data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4802
if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4915
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4919
if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4920
REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4921
REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4934
if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4937
if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4966
if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4967
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4971
if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4972
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4973
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4974
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5066
if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5067
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5068
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5069
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5085
if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5086
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5521
if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5538
if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6641
enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6642
se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6652
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6653
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6654
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6655
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6656
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6657
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6658
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6659
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6665
cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6666
sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6677
sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6693
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6694
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6695
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6696
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7042
return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2115
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2124
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2129
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2134
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2139
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2144
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4114
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4161
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4906
if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6865
sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6872
ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6884
sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6892
ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
710
sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
718
ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
731
sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
740
ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
754
sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
762
ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
775
sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
784
ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
798
sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
807
ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
992
if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
993
REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
994
REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1729
if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1730
REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1731
REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1420
if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2409
if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2456
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
794
return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
933
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
942
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
947
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
952
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
957
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
962
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
102
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
105
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
83
u32 cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
93
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
96
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
99
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
101
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
104
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
107
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
85
u32 cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
95
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
98
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c
100
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c
54
seg_size = REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c
58
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, PF_MAX_REGION);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c
61
seg_size = REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c
65
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c
96
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
602
seg_size = REG_GET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
606
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
621
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
101
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
79
u32 cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
89
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
92
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
95
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
98
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
101
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
104
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
82
u32 cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
92
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
95
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
98
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
100
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
78
u32 cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
88
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
91
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
94
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
97
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
100
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
103
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
81
u32 cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
91
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
94
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
97
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
544
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
552
size = (REG_GET_FIELD(viewport,
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
554
REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
535
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
543
size = (REG_GET_FIELD(viewport,
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
545
REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
616
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
617
u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
622
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
627
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
76
if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
802
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
807
size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
808
REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
100
if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1290
vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1295
u32 protections = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1300
info->mc_id = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
199
running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
222
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
228
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
335
if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
341
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
772
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
773
u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
779
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
784
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
971
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
976
size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
977
REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1006
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1007
u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1013
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1018
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1079
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1084
size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1085
REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1478
vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1483
u32 protections = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1488
info->mc_id = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
182
if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
309
running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
332
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
338
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
521
if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
527
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1350
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1359
size = (REG_GET_FIELD(viewport,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1361
REG_GET_FIELD(viewport,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1367
size = (REG_GET_FIELD(viewport,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1369
REG_GET_FIELD(viewport,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1375
size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1376
REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
663
cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
664
rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
665
fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
732
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
735
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
738
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
741
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
197
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
203
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
343
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
358
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
444
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
448
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
415
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
419
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
415
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
419
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
290
inst_index = REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_INDEX);
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
295
val = REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES) << 18 |
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
296
REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES) << 19 |
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
297
REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES) << 20 |
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
298
REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX) << 21 |
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
299
REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX) << 25 |
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
822
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
826
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
830
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
834
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
1388
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
1392
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
964
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
968
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1322
if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1323
REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1324
REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
146
cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
148
rw = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
176
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
179
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
182
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
185
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
107
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
110
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
113
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
116
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
85
cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
87
rw = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
102
cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
104
rw = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
123
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
126
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
129
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
132
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
109
cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
111
rw = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
131
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
134
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
137
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
140
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
102
cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
104
rw = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
116
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
119
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
122
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
125
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
193
cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
195
rw = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
222
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
225
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
228
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
231
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
115
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
118
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
121
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
124
REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
95
cid = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
97
rw = REG_GET_FIELD(status,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
1685
if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
1686
REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
1687
REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
420
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
428
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
309
rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET);
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
520
if (REG_GET_FIELD(bif_doorbell_int_cntl,
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
354
rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET);
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
600
if (REG_GET_FIELD(bif_doorbell_int_cntl,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
374
if (REG_GET_FIELD(bif_doorbell_intr_cntl,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
431
if (REG_GET_FIELD(bif_doorbell_intr_cntl,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
598
corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
599
fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
600
non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
631
if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
398
px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
409
tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
421
tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
528
if (REG_GET_FIELD(bif_doorbell_intr_cntl,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
53
tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
574
if (REG_GET_FIELD(bif_doorbell_intr_cntl,
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1263
if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1264
REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1282
if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1283
REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1721
if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT))
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1580
if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1489
if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
737
if ((REG_GET_FIELD(ic_op_cntl, SDMA0_IC_OP_CNTL, ICACHE_PRIMED) == 1) &&
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
738
(REG_GET_FIELD(sdma_status, SDMA0_STATUS_REG, UCODE_INIT_DONE) == 1))
sys/dev/pci/drm/amd/amdgpu/si.c
1633
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/si.c
1634
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
189
} while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
197
if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
202
if (REG_GET_FIELD(reg_c_tx_abrt_source,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
208
} else if (REG_GET_FIELD(reg_c_tx_abrt_source,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
233
if (REG_GET_FIELD(reg_c_tx_abrt_source,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
251
} while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
299
if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
423
data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
470
if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
471
(REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
477
} else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
486
if (REG_GET_FIELD(reg_ic_clr_activity,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
90
if (REG_GET_FIELD(en_stat, CKSVII2C_IC_ENABLE_STATUS, IC_EN))
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c
103
socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c
120
data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c
137
data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c
86
die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c
43
die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c
60
socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c
79
data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, PKG_TYPE);
sys/dev/pci/drm/amd/amdgpu/soc15.c
795
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/soc15.c
796
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/soc15.c
844
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/soc15.c
845
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
199
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
205
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
361
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
376
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
100
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1));
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
108
return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
109
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
110
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
111
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 0) ||
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
113
((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0x5 ||
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
114
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0xb) &&
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
361
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
536
hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
537
mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
551
err_addr = REG_GET_FIELD(addr,
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
78
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val),
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
79
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison),
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
80
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred),
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
81
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC),
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
82
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC),
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
83
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC)
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
87
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
88
((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) ||
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
89
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison) == 1)));
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
97
return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
98
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
99
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.h
85
#define MCA_IPID_2_DIE_ID(ipid) ((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) >> 2) & 0x03)
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.h
88
(MCA_IPID_LO_2_UMC_CH(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.h
91
(MCA_IPID_LO_2_UMC_INST(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.h
94
(((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo) & 0x1) << 2) | \
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.h
95
(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) & 0x03))
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
204
(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
214
(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
220
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
221
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
222
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
245
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
246
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
247
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
248
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
249
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
250
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
331
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
332
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
336
lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
337
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
82
return REG_GET_FIELD(rsmu_umc_val,
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
110
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
111
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) {
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
122
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
151
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
152
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
153
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
154
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
155
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
156
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) {
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
241
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
242
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
245
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
288
(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
298
(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
304
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
305
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) {
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
322
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
349
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
350
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
351
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
352
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
353
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
354
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) {
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
468
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
469
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
472
REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
502
return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_EccCtrl, UCFatalEn);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
66
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
118
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
119
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
134
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
135
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
136
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
137
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
138
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
139
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
222
addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
269
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
270
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
271
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
275
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
369
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
370
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
371
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
372
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
373
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
374
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) {
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
424
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
425
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
426
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1)) {
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
429
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c
73
(REG_GET_FIELD(ecc_err_cnt, UMCCH0_GeccErrCnt, GeccErrCnt) -
sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c
88
(REG_GET_FIELD(ecc_err_cnt, UMCCH0_GeccErrCnt, GeccUnCorrErrCnt) -
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
149
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
150
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
153
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
259
(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) -
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
269
(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) -
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
275
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
276
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
277
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
292
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
293
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
294
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
295
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
296
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
297
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
351
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
352
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
356
lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
357
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
64
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
65
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
81
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
82
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
83
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
84
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
85
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
86
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1174
if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1175
REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
2172
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
2288
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1970
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1597
poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
349
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
357
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
430
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
438
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
sys/dev/pci/drm/amd/amdgpu/vi.c
1390
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/vi.c
1391
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/vi.c
1420
if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
sys/dev/pci/drm/amd/amdgpu/vi.c
555
if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
sys/dev/pci/drm/amd/amdgpu/vi.c
559
if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
216
encoding = REG_GET_FIELD(context_id1,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
223
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
227
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
231
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
235
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
239
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
243
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
252
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
256
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
260
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
264
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
268
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
272
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
276
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
289
sq_intr_err_type = REG_GET_FIELD(context_id0, KFD_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
294
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
298
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
302
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
306
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
310
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
314
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
318
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
157
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
159
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, WLT),
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
160
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
162
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
164
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
166
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
168
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
170
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
172
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
182
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, DATA),
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
183
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
185
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV),
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
186
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
188
REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
190
REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
200
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
202
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
204
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
206
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
208
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
210
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
212
REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
377
sq_int_enc = REG_GET_FIELD(context_id1,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
385
sq_int_priv = REG_GET_FIELD(context_id0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
395
sq_int_errtype = REG_GET_FIELD(context_id0,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
380
encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING);
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
386
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
390
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
394
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
398
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
402
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
406
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
410
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
414
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
418
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
422
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
431
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
435
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
439
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
443
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
447
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
451
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
455
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
469
sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE);
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
473
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
477
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
481
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
485
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
489
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
493
REG_GET_FIELD(
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
497
REG_GET_FIELD(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
649
num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
651
num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
104
REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
132
REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
135
REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
263
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
74
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
76
duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
124
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
126
duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
152
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1243
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1300
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1302
duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2990
smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
3000
smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1184
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1248
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1250
duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1110
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2603
return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3338
info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3339
info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3346
instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3347
instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3400
hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3401
mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3427
if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3486
if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3492
REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3493
REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3498
*count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3510
if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3516
REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3517
REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3524
*count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3534
instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3554
instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3563
errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);