sys/dev/pci/drm/i915/gt/intel_ring_submission.c

128

ENGINE_WRITE_FW(engine, RING_INSTPM,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

132

RING_INSTPM(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

723

*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

64

{ RING_INSTPM(0), 0, 0, "INSTPM" }, \

sys/dev/pci/drm/i915/gvt/handlers.c

2257

MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

sys/dev/pci/drm/i915/gvt/mmio_context.c

139

{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

85

{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

sys/dev/pci/drm/i915/i915_gpu_error.c

1400

ee->instpm = ENGINE_READ(engine, RING_INSTPM);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

104

MMIO_RING_D(RING_INSTPM);