sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

427

ENGINE_WRITE(engine, RING_IMR,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

431

ENGINE_POSTING_READ(engine, RING_IMR);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

438

ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

444

ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

447

ENGINE_POSTING_READ(engine, RING_IMR);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

454

ENGINE_WRITE(engine, RING_IMR, ~0);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2116

ENGINE_READ(engine, RING_IMR));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3261

ENGINE_WRITE(engine, RING_IMR,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3263

ENGINE_POSTING_READ(engine, RING_IMR);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3268

ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

405

ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false);

sys/dev/pci/drm/i915/gvt/handlers.c

2208

MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

67

MMIO_RING_D(RING_IMR);