sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2948

RING_HWS_PGA,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2950

ENGINE_POSTING_READ(engine, RING_HWS_PGA);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

111

hwsp = RING_HWS_PGA(engine->mmio_base);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

404

ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

73

{ RING_HWS_PGA(0), 0, 0, "HWS" }, \

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4411

RING_HWS_PGA,

sys/dev/pci/drm/i915/gvt/handlers.c

2562

MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);

sys/dev/pci/drm/i915/i915_gpu_error.c

1434

mmio = RING_HWS_PGA(engine->mmio_base);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

829

MMIO_RING_D(RING_HWS_PGA);