RING_HEAD
ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR,
intel_uncore_write(uncore, RING_HEAD(base), 0);
ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));
ENGINE_POSTING_READ(engine, RING_HEAD);
ENGINE_WRITE_FW(engine, RING_HEAD, 0);
return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;
ENGINE_POSTING_READ(engine, RING_HEAD);
ENGINE_WRITE_FW(engine, RING_HEAD, ring->head);
if (ENGINE_READ_FW(engine, RING_HEAD) == ring->head)
if (ENGINE_READ_FW(engine, RING_HEAD) != ENGINE_READ_FW(engine, RING_TAIL)) {
ENGINE_READ_FW(engine, RING_HEAD),
ENGINE_READ(engine, RING_HEAD), ring->head,
ENGINE_READ_FW(engine, RING_HEAD),
ENGINE_READ_FW(engine, RING_HEAD),
i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)),
{ RING_HEAD(0), 0, 0, "HEAD" }, \
MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
ee->head = ENGINE_READ(engine, RING_HEAD);
head = ENGINE_READ_FW(engine, RING_HEAD);
MMIO_RING_D(RING_HEAD);