Symbol: REG_WRITE
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
109
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
112
REG_WRITE(MP1_SMN_C2PMSG_83, param);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
115
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
115
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
118
REG_WRITE(MP1_SMN_C2PMSG_83, param);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
121
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
84
REG_WRITE(DAL_RESP_REG, 0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
87
REG_WRITE(DAL_ARG_REG, param_in);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
90
REG_WRITE(DAL_MSG_REG, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
84
REG_WRITE(DAL_RESP_REG, 0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
87
REG_WRITE(DAL_ARG_REG, param_in);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
90
REG_WRITE(DAL_MSG_REG, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
114
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
117
REG_WRITE(MP1_SMN_C2PMSG_83, param);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
120
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
119
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
122
REG_WRITE(MP1_SMN_C2PMSG_83, param);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
125
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
135
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
135
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
138
REG_WRITE(MP1_SMN_C2PMSG_83, param);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
141
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
154
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
150
REG_WRITE(MP1_SMN_C2PMSG_38, VBIOSSMC_Status_BUSY);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
153
REG_WRITE(MP1_SMN_C2PMSG_37, param);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
134
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
137
REG_WRITE(MP1_SMN_C2PMSG_83, param);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
140
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
138
REG_WRITE(DAL_RESP_REG, 0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
141
REG_WRITE(DAL_ARG_REG, param_in);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
144
REG_WRITE(DAL_MSG_REG, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
78
REG_WRITE(DAL_RESP_REG, 0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
81
REG_WRITE(DAL_ARG_REG, param_in);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
84
REG_WRITE(DAL_MSG_REG, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
153
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
156
REG_WRITE(MP1_SMN_C2PMSG_83, param);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
159
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
169
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
123
REG_WRITE(DAL_RESP_REG, 0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
126
REG_WRITE(DAL_ARG_REG, param_in);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
129
REG_WRITE(DAL_MSG_REG, msg_id);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
63
REG_WRITE(DAL_RESP_REG, 0);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
66
REG_WRITE(DAL_ARG_REG, param_in);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
69
REG_WRITE(DAL_MSG_REG, msg_id);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
583
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
584
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
605
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
606
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
625
REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
626
REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
634
REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
635
REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
220
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
221
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
244
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
245
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
219
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
220
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
242
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
243
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1391
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1392
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1437
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1438
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2314
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2315
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2340
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2341
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
115
REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
665
REG_WRITE(DP_DTO_PHASE[params->otg_inst], dto_phase_hz);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
666
REG_WRITE(DP_DTO_MODULO[params->otg_inst], dto_modulo_hz);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
115
REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
131
REG_WRITE(BIOS_SCRATCH_2, s2);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
142
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
143
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
144
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
145
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
146
REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
70
REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
854
REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
141
REG_WRITE(AUX_CONTROL, value);
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
155
REG_WRITE(AUX_CONTROL, value);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1298
REG_WRITE(MODULO[inst],
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1313
REG_WRITE(PHASE[inst], pixel_clk);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1314
REG_WRITE(MODULO[inst], ref_clk);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1343
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1344
REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1347
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1348
REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
989
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
990
REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
993
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
994
REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
118
REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
344
REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
366
REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
416
REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
419
REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
421
REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
493
REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
496
REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
535
REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
842
REG_WRITE(MASTER_COMM_DATA_REG1, header);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
843
REG_WRITE(MASTER_COMM_DATA_REG2, data1);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
844
REG_WRITE(MASTER_COMM_DATA_REG3, data2);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
93
REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
96
REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
280
REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
320
REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
333
REG_WRITE(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
335
REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
337
REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
102
REG_WRITE(BL_PWM_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
104
REG_WRITE(BL_PWM_CNTL2,
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
106
REG_WRITE(BL_PWM_PERIOD_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
125
REG_WRITE(BL_PWM_CNTL, 0x8000FA00);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
126
REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
133
REG_WRITE(BIOS_SCRATCH_2, value);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
120
REG_WRITE(AFMT_GENERIC_0, *content++);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
121
REG_WRITE(AFMT_GENERIC_1, *content++);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
122
REG_WRITE(AFMT_GENERIC_2, *content++);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
123
REG_WRITE(AFMT_GENERIC_3, *content++);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
124
REG_WRITE(AFMT_GENERIC_4, *content++);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
125
REG_WRITE(AFMT_GENERIC_5, *content++);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
126
REG_WRITE(AFMT_GENERIC_6, *content++);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
127
REG_WRITE(AFMT_GENERIC_7, *content);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
447
REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
740
REG_WRITE(AFMT_AVI_INFO0, content[0]);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
742
REG_WRITE(AFMT_AVI_INFO1, content[1]);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
744
REG_WRITE(AFMT_AVI_INFO2, content[2]);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
746
REG_WRITE(AFMT_AVI_INFO3, content[3]);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1460
REG_WRITE(REGAMMA_LUT_INDEX, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1465
REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1466
REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1467
REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1468
REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1469
REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1470
REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
158
REG_WRITE(SCL_SCALER_ENABLE, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
161
REG_WRITE(SCL_TAP_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
162
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
163
REG_WRITE(SCL_F_SHARP_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
171
REG_WRITE(SCL_SCALER_ENABLE, 1);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
262
REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
361
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
390
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
426
REG_WRITE(SCL_F_SHARP_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
508
REG_WRITE(SCL_UPDATE, 0x00010000);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
511
REG_WRITE(SCL_F_SHARP_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
535
REG_WRITE(SCL_VERT_FILTER_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
549
REG_WRITE(SCL_HORZ_FILTER_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
573
REG_WRITE(SCL_UPDATE, 0);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
82
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x3);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
83
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x1);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
84
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x3);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
85
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x1);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
86
REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x1);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c
103
REG_WRITE(VPG_GENERIC_PACKET_DATA, *content++);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
110
REG_WRITE(BL_PWM_CNTL,
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
112
REG_WRITE(BL_PWM_CNTL2,
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
114
REG_WRITE(BL_PWM_PERIOD_CNTL,
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
123
REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
124
REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
213
REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
250
REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
110
REG_WRITE(AFMT_GENERIC_0, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
111
REG_WRITE(AFMT_GENERIC_1, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
112
REG_WRITE(AFMT_GENERIC_2, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
113
REG_WRITE(AFMT_GENERIC_3, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
114
REG_WRITE(AFMT_GENERIC_4, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
115
REG_WRITE(AFMT_GENERIC_5, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
116
REG_WRITE(AFMT_GENERIC_6, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
117
REG_WRITE(AFMT_GENERIC_7, *content);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
413
REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
838
REG_WRITE(AFMT_GENERIC_0, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
839
REG_WRITE(AFMT_GENERIC_1, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
840
REG_WRITE(AFMT_GENERIC_2, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
841
REG_WRITE(AFMT_GENERIC_3, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
842
REG_WRITE(AFMT_GENERIC_4, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
843
REG_WRITE(AFMT_GENERIC_5, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
844
REG_WRITE(AFMT_GENERIC_6, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
845
REG_WRITE(AFMT_GENERIC_7, *content);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
260
REG_WRITE(AFMT_GENERIC_0, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
261
REG_WRITE(AFMT_GENERIC_1, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
262
REG_WRITE(AFMT_GENERIC_2, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
263
REG_WRITE(AFMT_GENERIC_3, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
264
REG_WRITE(AFMT_GENERIC_4, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
265
REG_WRITE(AFMT_GENERIC_5, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
266
REG_WRITE(AFMT_GENERIC_6, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
267
REG_WRITE(AFMT_GENERIC_7, *content++);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
654
REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
185
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub1->debug_test_index_pstate);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
272
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
297
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
322
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
347
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
650
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, 0x6);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
689
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
408
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
409
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
410
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
413
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
414
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
415
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
418
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
419
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
420
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
423
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
424
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
425
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
428
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
429
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
430
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
433
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
434
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
435
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
438
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
439
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
440
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
1007
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub2->debug_test_index_pstate);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
833
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
834
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
835
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
838
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
839
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
840
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
843
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
844
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
845
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
848
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
849
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
850
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
853
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
854
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
855
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
858
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
859
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
860
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
863
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
864
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
865
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
868
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
869
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
870
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
873
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
874
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
875
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
344
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
345
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
346
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
349
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
350
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
351
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
354
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
355
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
356
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
359
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
360
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
361
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
364
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
365
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
366
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
369
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
370
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
371
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
374
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
375
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
376
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
379
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
380
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
381
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
384
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
385
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
386
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
389
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
390
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
391
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
394
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
395
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
396
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
503
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
506
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
509
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
512
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
515
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
518
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
521
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
522
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
523
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
524
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
525
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
526
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
527
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
530
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
531
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
532
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
533
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
534
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
535
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
536
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
539
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
542
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
544
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
547
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
549
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B, reg);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
138
REG_WRITE(HUBPREQ_DEBUG_DB, value);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
178
REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
676
REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
714
REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]);
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
813
REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
402
REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
501
REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
170
REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
256
REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
49
REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part);
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
83
REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1884
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1888
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1890
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
869
REG_WRITE(D1VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
870
REG_WRITE(D2VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
871
REG_WRITE(D3VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
872
REG_WRITE(D4VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3150
REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3151
REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3158
REG_WRITE(REFCLK_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
366
REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
375
REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
378
REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
384
REG_WRITE(D1VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
385
REG_WRITE(D2VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
386
REG_WRITE(D3VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
387
REG_WRITE(D4VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
388
REG_WRITE(D5VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
389
REG_WRITE(D6VGA_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
362
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
366
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
368
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
796
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
800
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
802
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
240
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
251
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
253
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
954
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
958
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
960
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
275
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
325
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
329
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
331
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1312
REG_WRITE(MPC_OUT_CSC_COEF_FORMAT, 0);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1353
REG_WRITE(MPC_OUT_CSC_COEF_FORMAT, 0);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
269
REG_WRITE(DPG_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
270
REG_WRITE(DPG_COLOUR_R_CR, 0);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
271
REG_WRITE(DPG_COLOUR_G_Y, 0);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
272
REG_WRITE(DPG_COLOUR_B_CB, 0);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
273
REG_WRITE(DPG_RAMP_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1080
REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1204
REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1207
REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1218
REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1219
REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1220
REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1476
REG_WRITE(OTG_CRC_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
743
REG_WRITE(OTG_TRIGA_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
171
REG_WRITE(OTG_H_TIMING_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
193
REG_WRITE(OTG_CRC_CNTL, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
342
REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
343
REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
382
REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
383
REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
402
REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
403
REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
427
REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
428
REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
139
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
140
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
141
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
142
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
143
REG_WRITE(DMCUB_SCRATCH0, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
149
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
169
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
170
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
171
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
178
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
179
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
180
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
206
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
207
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
208
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
213
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
214
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
215
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
216
REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
221
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
222
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
223
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
233
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
234
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
235
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
240
REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
241
REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
250
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
251
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
252
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
257
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
258
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
266
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
267
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
268
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
279
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
281
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
283
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
298
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
306
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
308
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, 0x80002000);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
310
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
328
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
334
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
336
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
346
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
370
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
401
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
409
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
102
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
103
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
104
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
111
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
112
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
113
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
137
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
138
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
139
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
144
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
145
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
146
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
147
REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
152
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
153
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
154
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
163
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
164
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
165
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
170
REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
171
REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
180
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
181
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
182
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
187
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
188
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
196
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
197
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
198
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
136
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
137
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
138
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
139
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
140
REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
141
REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
142
REG_WRITE(DMCUB_SCRATCH0, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
152
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
170
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
171
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
172
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
179
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
180
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
181
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
202
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
203
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
204
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
211
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
212
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
213
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
220
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
221
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
222
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
227
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
228
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
236
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
237
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
238
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
247
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
248
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
263
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
269
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
270
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
288
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
319
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
344
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
384
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
392
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
398
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
400
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
410
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
136
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
137
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
138
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
139
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
140
REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
141
REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
142
REG_WRITE(DMCUB_SCRATCH0, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
152
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
170
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
171
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
172
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
179
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
180
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
181
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
200
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
201
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
202
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
209
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
210
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
211
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
232
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
233
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
234
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
241
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
242
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
243
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
250
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
251
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
252
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
257
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
258
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
266
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
267
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
268
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
277
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
278
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
293
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
299
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
300
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
318
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
344
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
369
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
392
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
400
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
406
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
408
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
418
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
503
REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
508
REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
513
REG_WRITE(DMCUB_SCRATCH17, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
528
REG_WRITE(DMCUB_SCRATCH9, addr->grph.addr.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
529
REG_WRITE(DMCUB_SCRATCH11, addr->grph.meta_addr.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
531
REG_WRITE(DMCUB_SCRATCH12, addr->grph.addr.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
532
REG_WRITE(DMCUB_SCRATCH13, addr->grph.meta_addr.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
534
REG_WRITE(DMCUB_SCRATCH15, !index);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
538
REG_WRITE(DMCUB_SCRATCH18, addr->grph.addr.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
539
REG_WRITE(DMCUB_SCRATCH19, addr->grph.meta_addr.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
541
REG_WRITE(DMCUB_SCRATCH20, addr->grph.addr.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
542
REG_WRITE(DMCUB_SCRATCH22, addr->grph.meta_addr.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
544
REG_WRITE(DMCUB_SCRATCH23, !index);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
135
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
136
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
137
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
138
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
139
REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
140
REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
141
REG_WRITE(DMCUB_SCRATCH0, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
150
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
173
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
174
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
175
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
182
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
183
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
184
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
201
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
202
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
203
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
208
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
209
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
210
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
229
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
230
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
231
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
238
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
239
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
240
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
247
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
248
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
249
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
254
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
255
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
263
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
264
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
265
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
272
REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
273
REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
283
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
284
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
299
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
305
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
306
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
324
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
350
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
375
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
422
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
430
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
436
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
438
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
448
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
533
REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
545
REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
550
REG_WRITE(DMCUB_SCRATCH17, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
105
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
106
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
107
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
108
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
109
REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
110
REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
111
REG_WRITE(DMCUB_SCRATCH0, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
121
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
142
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
143
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
144
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
151
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
152
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
153
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
176
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
177
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
178
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
185
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
186
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
187
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
209
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
210
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
211
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
218
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
219
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
220
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
227
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
228
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
229
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
234
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
235
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
243
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
244
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
245
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
252
REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
253
REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
263
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
264
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
279
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
285
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
286
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
304
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
330
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
355
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
380
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
388
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
394
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
396
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
406
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
497
REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
502
REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
507
REG_WRITE(DMCUB_SCRATCH17, 0);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
531
REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
534
REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
537
REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
540
REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
543
REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
546
REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
549
REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
552
REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
555
REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
558
REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
561
REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
564
REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
567
REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
570
REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
573
REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
581
REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
645
REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp);