sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

182

REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

209

REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

212

REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

421

REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

468

REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

637

REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

589

REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

226

REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

225

REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1397

REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2320

REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

116

REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

106

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

134

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

206

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

66

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

80

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

146

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

157

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

221

REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

350

REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

115

REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

139

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

233

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

310

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

341

REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

363

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

376

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

413

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

431

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

491

REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

504

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

514

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

532

REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

560

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

671

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

718

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

736

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

777

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

786

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

800

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

809

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

837

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

850

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

91

REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

948

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

993

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

330

REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

763

REG_WAIT(DMIF_BUFFER_CONTROL,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

800

REG_WAIT(DMIF_BUFFER_CONTROL,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

646

REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10);

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

249

REG_WAIT(BL_PWM_GRP1_REG_LOCK,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

719

REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

87

REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

935

REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

231

REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

94

REG_WAIT(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, 1, 20, 100);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

72

REG_WAIT(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.c

54

REG_WAIT(APG_CONTROL,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.c

58

REG_WAIT(APG_CONTROL,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

652

REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

795

REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

80

REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

808

REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

851

REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

942

REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

239

REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

516

REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

351

REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

62

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

299

REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

314

REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

323

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

327

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

404

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

331

REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

389

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

324

REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

350

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

354

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

166

REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

576

REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

593

REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

610

REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

135

REG_WAIT(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, 0, 1, 5);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

158

REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

267

REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

186

REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

378

REG_WAIT(DP_DPHY_SYM32_STATUS,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

434

REG_WAIT(DP_DPHY_SYM32_STATUS,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

107

REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

112

REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL, /* Disable Clock Ramp Adjuster FIFO */

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

121

REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

126

REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

153

REG_WAIT(DP_SYM32_ENC_VID_STREAM_CONTROL,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

73

REG_WAIT(DP_SYM32_ENC_CONTROL,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

81

REG_WAIT(DP_SYM32_ENC_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

101

REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

118

REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1000, 30);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

121

REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1000, 30);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

124

REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1000, 30);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

127

REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1000, 30);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

141

REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

142

REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

143

REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

144

REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

147

REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

148

REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

149

REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

150

REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

81

REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

82

REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

83

REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

84

REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1158

REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1159

REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1160

REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1161

REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1179

REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100000); /* 1 vupdate at 10hz */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1182

REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100000);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1185

REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100000);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1188

REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100000);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1353

REG_WAIT(HUBPRET_READ_LINE_STATUS,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

60

REG_WAIT(DCHUBP_CNTL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

976

REG_WAIT(DCHUBP_CNTL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

102

REG_WAIT(DCHUBP_CNTL,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

912

REG_WAIT(DOMAIN1_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

920

REG_WAIT(DOMAIN3_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

928

REG_WAIT(DOMAIN5_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

936

REG_WAIT(DOMAIN7_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

973

REG_WAIT(DOMAIN0_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

981

REG_WAIT(DOMAIN2_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

989

REG_WAIT(DOMAIN4_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

997

REG_WAIT(DOMAIN6_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

498

REG_WAIT(DOMAIN16_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

506

REG_WAIT(DOMAIN17_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

514

REG_WAIT(DOMAIN18_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

522

REG_WAIT(DOMAIN19_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

530

REG_WAIT(DOMAIN20_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

538

REG_WAIT(DOMAIN21_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

569

REG_WAIT(DOMAIN1_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

577

REG_WAIT(DOMAIN3_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

585

REG_WAIT(DOMAIN5_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

593

REG_WAIT(DOMAIN7_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

601

REG_WAIT(DOMAIN9_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

651

REG_WAIT(DOMAIN0_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

659

REG_WAIT(DOMAIN2_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

667

REG_WAIT(DOMAIN4_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

675

REG_WAIT(DOMAIN6_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

683

REG_WAIT(DOMAIN8_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

117

REG_WAIT(DOMAIN0_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

125

REG_WAIT(DOMAIN2_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

133

REG_WAIT(DOMAIN4_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

141

REG_WAIT(DOMAIN6_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

149

REG_WAIT(DOMAIN8_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

180

REG_WAIT(DOMAIN16_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

188

REG_WAIT(DOMAIN17_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

196

REG_WAIT(DOMAIN18_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

204

REG_WAIT(DOMAIN19_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

212

REG_WAIT(DOMAIN20_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

60

REG_WAIT(DOMAIN1_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

68

REG_WAIT(DOMAIN3_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

76

REG_WAIT(DOMAIN5_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

84

REG_WAIT(DOMAIN7_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

92

REG_WAIT(DOMAIN9_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

308

REG_WAIT(DOMAIN16_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

316

REG_WAIT(DOMAIN17_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

324

REG_WAIT(DOMAIN18_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

465

REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

469

REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

473

REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

477

REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

251

REG_WAIT(DOMAIN16_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

259

REG_WAIT(DOMAIN17_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

267

REG_WAIT(DOMAIN18_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

275

REG_WAIT(DOMAIN19_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

570

REG_WAIT(DOMAIN1_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

578

REG_WAIT(DOMAIN3_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

586

REG_WAIT(DOMAIN5_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

594

REG_WAIT(DOMAIN7_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

103

REG_WAIT(DOMAIN17_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

111

REG_WAIT(DOMAIN18_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

119

REG_WAIT(DOMAIN19_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

177

REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

181

REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

185

REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

189

REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

95

REG_WAIT(DOMAIN16_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

94

REG_WAIT(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, 1, 20, 100);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

114

REG_WAIT(MPCC_STATUS[id],

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

481

REG_WAIT(MPCC_STATUS[id],

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

185

REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

835

REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

836

REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

846

REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

847

REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

696

REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

697

REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

79

REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

491

REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

499

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

570

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

680

REG_WAIT(OTG_MASTER_UPDATE_LOCK,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

838

REG_WAIT(OTG_STATUS,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

844

REG_WAIT(OTG_STATUS,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

277

REG_WAIT(OTG_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

324

REG_WAIT(OTG_MASTER_UPDATE_LOCK,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

351

REG_WAIT(OTG_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

392

REG_WAIT(OTG_MASTER_UPDATE_LOCK,

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

52

REG_WAIT(OTG_MASTER_UPDATE_LOCK,

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

128

REG_WAIT(OTG_MASTER_UPDATE_LOCK,

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

340

REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, 0, 2, 100000); /* 1 vupdate at 5hz */

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

58

REG_WAIT(OTG_MASTER_UPDATE_LOCK,

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

145

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

168

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

145

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

160

REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

128

REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING, 0, 2, 50000);

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

195

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

210

REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

162

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

165

REG_WAIT(OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

180

REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

445

REG_WAIT(OTG_CLOCK_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

230

REG_WAIT(OTG_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

235

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

250

REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

455

REG_WAIT(OTG_MASTER_UPDATE_LOCK,

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

108

REG_WAIT(DOMAIN16_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

116

REG_WAIT(DOMAIN17_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

124

REG_WAIT(DOMAIN18_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

132

REG_WAIT(DOMAIN19_PG_STATUS,

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

207

REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

212

REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

217

REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

222

REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

281

REG_WAIT(DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

329

REG_WAIT(DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

432

REG_WAIT(DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);