sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

631

REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

639

REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

647

REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

655

REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

242

value = REG_UPDATE_4(AUX_SW_DATA,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

186

REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

621

REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

152

REG_UPDATE_4(DP_DPHY_CNTL,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

622

REG_UPDATE_4(PRESCALE_GRPH_CONTROL,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

123

REG_UPDATE_4(DP_DPHY_CNTL,

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

579

REG_UPDATE_4(DP_PIXEL_FORMAT,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

110

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

119

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

128

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

133

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

142

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

147

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

156

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

161

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

170

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

175

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

184

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

189

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

198

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

203

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

235

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

251

REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

674

REG_UPDATE_4(DP_SYM32_ENC_SDP_AUDIO_CONTROL0,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

94

REG_UPDATE_4(DCHVM_CLK_CTRL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

156

REG_UPDATE_4(DCSURF_TILING_CONFIG,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

418

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

528

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

542

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

321

REG_UPDATE_4(DCSURF_TILING_CONFIG,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

416

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

430

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

625

REG_UPDATE_4(CURSOR_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

786

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

138

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

268

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

324

REG_UPDATE_4(DCSURF_ADDR_CONFIG,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

359

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

133

REG_UPDATE_4(CURSOR_CONTROL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

487

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

260

REG_UPDATE_4(DPG_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1033

REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1133

REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

460

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

86

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

209

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

218

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

264

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

222

REG_UPDATE_4(OTG_CRC_CNTL,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

255

REG_UPDATE_4(OTG_CRC_CNTL,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

289

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

332

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

361

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

373

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

393

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

306

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

362

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,