Symbol: REG_UPDATE_2
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
113
REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
125
REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
124
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
134
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
186
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
189
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
195
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
198
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
204
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
207
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
213
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
216
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
235
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
239
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
244
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
248
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
253
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
257
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
262
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
266
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
288
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
293
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
312
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
317
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
339
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
344
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
365
REG_UPDATE_2(DSCCLK0_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
372
REG_UPDATE_2(DSCCLK1_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
379
REG_UPDATE_2(DSCCLK2_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
387
REG_UPDATE_2(DSCCLK3_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
407
REG_UPDATE_2(DSCCLK0_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
414
REG_UPDATE_2(DSCCLK1_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
421
REG_UPDATE_2(DSCCLK2_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
431
REG_UPDATE_2(DSCCLK3_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
454
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
461
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
471
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
478
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
488
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
495
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
505
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
512
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
522
REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
529
REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
123
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
128
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
133
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
138
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
166
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
175
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
184
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
193
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
240
REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
263
REG_UPDATE_2(DPSTREAMCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
268
REG_UPDATE_2(DPSTREAMCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
273
REG_UPDATE_2(DPSTREAMCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
278
REG_UPDATE_2(DPSTREAMCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
123
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
128
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
133
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
138
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
165
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
174
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
183
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
192
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
239
REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
290
REG_UPDATE_2(DPSTREAMCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
295
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
299
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
303
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1280
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1285
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1290
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1295
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1322
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1331
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1340
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1349
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1458
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1464
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1470
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1476
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1583
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1587
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1594
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1598
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1605
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1609
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1616
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1620
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1627
REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1631
REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1701
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1712
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1723
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1734
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
181
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1810
REG_UPDATE_2(DSCCLK0_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1818
REG_UPDATE_2(DSCCLK1_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1826
REG_UPDATE_2(DSCCLK2_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1834
REG_UPDATE_2(DSCCLK3_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1856
REG_UPDATE_2(DSCCLK0_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
186
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1864
REG_UPDATE_2(DSCCLK1_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1872
REG_UPDATE_2(DSCCLK2_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1880
REG_UPDATE_2(DSCCLK3_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
191
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1933
REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1940
REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1947
REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1954
REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
196
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1961
REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2008
REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2015
REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2022
REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2029
REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2036
REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
218
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
223
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2336
REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
435
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
440
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
445
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
450
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
472
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
477
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
482
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
487
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
532
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
537
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
542
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
547
REG_UPDATE_2(SYMCLK32_SE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
583
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
588
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
635
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
640
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
645
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
650
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
669
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
675
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
682
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
689
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
709
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
715
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
721
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
727
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
733
REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
753
REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
758
REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
763
REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
768
REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
773
REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
820
REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
825
REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
830
REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
835
REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
840
REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
229
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
238
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
247
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
256
REG_UPDATE_2(DTBCLK_P_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
279
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
286
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
296
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
303
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
313
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
320
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
330
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
337
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
392
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
395
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
401
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
404
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
410
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
413
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
419
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
422
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
441
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
445
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
450
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
454
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
459
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
463
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
468
REG_UPDATE_2(SYMCLK32_LE_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
472
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
490
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
493
REG_UPDATE_2(DPSTREAMCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
499
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
502
REG_UPDATE_2(DPSTREAMCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
508
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
511
REG_UPDATE_2(DPSTREAMCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
517
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
520
REG_UPDATE_2(DPSTREAMCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
529
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
543
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
551
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
559
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
567
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
692
REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
736
REG_UPDATE_2(DSCCLK0_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
743
REG_UPDATE_2(DSCCLK1_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
749
REG_UPDATE_2(DSCCLK2_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
755
REG_UPDATE_2(DSCCLK3_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
774
REG_UPDATE_2(DSCCLK0_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
780
REG_UPDATE_2(DSCCLK1_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
786
REG_UPDATE_2(DSCCLK2_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
792
REG_UPDATE_2(DSCCLK3_DTO_PARAM,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
807
REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
814
REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
821
REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
828
REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
843
REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
848
REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
853
REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
858
REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
167
REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
210
REG_UPDATE_2(MASTER_COMM_CMD_REG,
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
73
REG_UPDATE_2(MASTER_COMM_CMD_REG,
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
1102
REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
1194
REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
1285
REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
237
REG_UPDATE_2(AUX_SW_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
87
REG_UPDATE_2(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1,
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1003
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1352
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
835
REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
999
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
337
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
352
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
487
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
499
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
87
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
99
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
255
REG_UPDATE_2(DC_I2C_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
421
REG_UPDATE_2(DC_I2C_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1530
REG_UPDATE_2(DP_MSE_SAT0,
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1544
REG_UPDATE_2(DP_MSE_SAT0,
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1558
REG_UPDATE_2(DP_MSE_SAT1,
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1572
REG_UPDATE_2(DP_MSE_SAT1,
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
338
REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
358
REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
675
REG_UPDATE_2(DP_SEC_CNTL1,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
158
REG_UPDATE_2(DVMM_PTE_ARB_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
287
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
291
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
328
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
355
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
385
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
418
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
618
REG_UPDATE_2(GRPH_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
156
REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
163
REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
168
REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
177
REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
227
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
231
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
237
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
311
REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
481
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
486
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
512
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
524
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
605
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
616
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
621
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
626
REG_UPDATE_2(
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
237
REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1269
REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1277
REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
132
REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1323
REG_UPDATE_2(AFMT_60958_0,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1364
REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1406
REG_UPDATE_2(DP_SEC_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
438
REG_UPDATE_2(
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
576
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
580
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
587
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
591
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
597
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
611
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
623
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
751
REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
759
REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1024
REG_UPDATE_2(LB_DATA_FORMAT,
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
125
REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1582
REG_UPDATE_2(DCFE_MEM_PWR_CTRL,
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1586
REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL,
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
107
REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
256
REG_UPDATE_2(WBSCL_MODE, WBSCL_MODE, params->out_format,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
78
REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, params->cnv_params.src_width,
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
51
REG_UPDATE_2(MUX[opp_id],
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c
181
REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c
59
REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c
66
REG_UPDATE_2(AFMT_60958_0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
152
REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8,
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c
64
REG_UPDATE_2(AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, 0, AFMT_MEM_PWR_FORCE, 1);
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c
74
REG_UPDATE_2(AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, 1, AFMT_MEM_PWR_FORCE, 0);
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c
59
REG_UPDATE_2(VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, 0, VPG_GSP_LIGHT_SLEEP_FORCE, 1);
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c
74
REG_UPDATE_2(VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, 1, VPG_GSP_LIGHT_SLEEP_FORCE, 0);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1254
REG_UPDATE_2(DP_MSE_SAT0,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1268
REG_UPDATE_2(DP_MSE_SAT0,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1282
REG_UPDATE_2(DP_MSE_SAT1,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1296
REG_UPDATE_2(DP_MSE_SAT1,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
268
REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
288
REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
527
REG_UPDATE_2(DP_SEC_CNTL1,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1263
REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1311
REG_UPDATE_2(AFMT_60958_0,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1354
REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1396
REG_UPDATE_2(DP_SEC_CNTL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
340
REG_UPDATE_2(DP_PIXEL_FORMAT,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
519
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
525
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
534
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
540
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
548
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
563
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
575
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
999
REG_UPDATE_2(DP_VID_TIMING,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
102
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
109
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
116
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
123
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
130
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
270
REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL1,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
287
REG_UPDATE_2(DP_DSC_CNTL,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
326
REG_UPDATE_2(DP_MSA_VBID_MISC,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
337
REG_UPDATE_2(DP_SEC_CNTL,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
385
REG_UPDATE_2(DME_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
509
REG_UPDATE_2(DP_VID_TIMING,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
81
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
88
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
95
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
103
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
110
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
117
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
124
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
131
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
138
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
145
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
152
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
159
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
166
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
173
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
180
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
310
REG_UPDATE_2(DP_DSC_CNTL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
361
REG_UPDATE_2(DP_MSA_VBID_MISC,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
633
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
637
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
644
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
648
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
654
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
667
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
679
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
82
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
89
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
96
REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
198
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
202
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
209
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
213
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
219
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
232
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
244
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
340
REG_UPDATE_2(DP_VID_TIMING,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
156
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
160
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
167
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
171
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
177
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
190
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
202
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
288
REG_UPDATE_2(DP_VID_TIMING,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
144
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
148
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
155
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
159
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
165
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
178
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
190
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
320
REG_UPDATE_2(DP_VID_TIMING,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
156
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
160
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
167
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
171
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
177
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
190
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
202
REG_UPDATE_2(HDMI_CONTROL,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
338
REG_UPDATE_2(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 1, DP_VID_STREAM_DIS_DEFER, 2);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
803
REG_UPDATE_2(DME_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
420
REG_UPDATE_2(CURSOR0_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
514
REG_UPDATE_2(DPP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1029
REG_UPDATE_2(CM_3DLUT_MODE,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1041
REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1296
REG_UPDATE_2(CM_3DLUT_MODE,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1308
REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
624
REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
811
REG_UPDATE_2(CM_BLNDGAM_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
49
REG_UPDATE_2(DPP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
54
REG_UPDATE_2(DPP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
62
REG_UPDATE_2(DPP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
238
REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
104
REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
90
REG_UPDATE_2(DSCC_MEM_POWER_CONTROL,
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
157
REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
71
REG_UPDATE_2(FC_SOURCE_SIZE, FC_SOURCE_WIDTH, params->cnv_params.src_width,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
179
REG_UPDATE_2(DWB_OGAM_LUT_CONTROL,
sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c
192
REG_UPDATE_2(ddc_setup,
sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c
76
REG_UPDATE_2(mux,
sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c
97
REG_UPDATE_2(toggle_filt_cntl,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
308
REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC0,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
322
REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC1,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
336
REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC2,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
350
REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC3,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
131
REG_UPDATE_2(DP_SYM32_ENC_VID_CRC_CONTROL,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
586
REG_UPDATE_2(DP_SYM32_ENC_VID_VBID_CONTROL,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
597
REG_UPDATE_2(DP_SYM32_ENC_SDP_GSP_CONTROL11,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
656
REG_UPDATE_2(DP_SYM32_ENC_SDP_AUDIO_CONTROL0,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
141
REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
207
REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
612
REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
99
REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
607
REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
396
REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
1001
REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
1027
REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
1046
REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
1012
REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
755
REG_UPDATE_2(DCHUBBUB_ARB_USR_RETRAINING_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
998
REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
289
REG_UPDATE_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 1,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
324
REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
525
REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
545
REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1181
REG_UPDATE_2(CURSOR_SIZE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
195
REG_UPDATE_2(DCSURF_SURFACE_PITCH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
199
REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
219
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
223
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
227
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
231
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
254
REG_UPDATE_2(HUBPRET_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
332
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
337
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
391
REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
46
REG_UPDATE_2(DCHUBP_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
365
REG_UPDATE_2(DCSURF_SURFACE_PITCH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
372
REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
392
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
396
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
400
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
404
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
455
REG_UPDATE_2(HUBPRET_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
533
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
538
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
621
REG_UPDATE_2(CURSOR_SIZE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
63
REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
759
REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
982
REG_UPDATE_2(DCHUBP_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
111
REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
129
REG_UPDATE_2(CURSOR_SIZE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
45
REG_UPDATE_2(UCLK_PSTATE_FORCE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
54
REG_UPDATE_2(UCLK_PSTATE_FORCE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
64
REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel,
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
155
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
160
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
113
REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, bias, HUBP0_3DLUT_FL_SCALE, scale);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
142
REG_UPDATE_2(_3DLUT_FL_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
146
REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
172
REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
175
REG_UPDATE_2(DCHUBP_MALL_CONFIG, MALL_PREF_CMD_TYPE, 1, MALL_PREF_MODE, 0);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
461
REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
530
REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
567
REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
577
REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
186
REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
196
REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
202
REG_UPDATE_2(DCHUB_FB_LOCATION,
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c
144
REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8,
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c
152
REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8,
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
118
REG_UPDATE_2(DENORM_CONTROL[opp_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
121
REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
124
REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
289
REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
125
REG_UPDATE_2(MUX[opp_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
194
REG_UPDATE_2(MPCC_OGAM_LUT_CONTROL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
436
REG_UPDATE_2(DENORM_CONTROL[opp_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
439
REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
442
REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
57
REG_UPDATE_2(MUX[opp_id], MPC_OUT_RATE_CONTROL_DISABLE,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
73
REG_UPDATE_2(MUX[mpcc_id], MPC_OUT_RATE_CONTROL_DISABLE,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
921
REG_UPDATE_2(RMU_3DLUT_MODE[rmu_idx],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
979
REG_UPDATE_2(RMU_3DLUT_READ_WRITE_CONTROL[rmu_idx],
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
132
REG_UPDATE_2(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
294
REG_UPDATE_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
807
REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
901
REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id],
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
213
REG_UPDATE_2(FMT_CLAMP_CNTL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
219
REG_UPDATE_2(FMT_CLAMP_CNTL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
224
REG_UPDATE_2(FMT_CLAMP_CNTL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
229
REG_UPDATE_2(FMT_CLAMP_CNTL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
235
REG_UPDATE_2(FMT_CLAMP_CNTL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
255
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
270
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
275
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
280
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
78
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
82
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
89
REG_UPDATE_2(FMT_CONTROL,
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
228
REG_UPDATE_2(DPG_CONTROL,
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
239
REG_UPDATE_2(DPG_CONTROL,
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
250
REG_UPDATE_2(DPG_CONTROL,
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
279
REG_UPDATE_2(DPG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1029
REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1274
REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1485
REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1490
REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1495
REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1500
REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1512
REG_UPDATE_2(OTG_CRC1_WINDOWA_X_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1517
REG_UPDATE_2(OTG_CRC1_WINDOWA_Y_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1522
REG_UPDATE_2(OTG_CRC1_WINDOWB_X_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1527
REG_UPDATE_2(OTG_CRC1_WINDOWB_Y_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
196
REG_UPDATE_2(OTG_H_SYNC_A,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
210
REG_UPDATE_2(OTG_H_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
234
REG_UPDATE_2(OTG_V_SYNC_A,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
248
REG_UPDATE_2(OTG_V_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
282
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
383
REG_UPDATE_2(CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
429
REG_UPDATE_2(OTG_BLANK_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
453
REG_UPDATE_2(OTG_BLANK_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
487
REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
496
REG_UPDATE_2(OTG_CLOCK_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
508
REG_UPDATE_2(OTG_CLOCK_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
512
REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
544
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
562
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
938
REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
315
REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
361
REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
417
REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
424
REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
440
REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
446
REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
69
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
106
REG_UPDATE_2(OTG_GLOBAL_CONTROL0,
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
109
REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
80
REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
83
REG_UPDATE_2(OTG_GLOBAL_CONTROL4,
sys/dev/pci/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
67
REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
110
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
159
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
194
REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
120
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
157
REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
160
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
207
REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
287
REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
127
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
177
REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
202
REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
207
REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
212
REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
217
REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
235
REG_UPDATE_2(OTG_CRC1_WINDOWA_X_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
240
REG_UPDATE_2(OTG_CRC1_WINDOWA_Y_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
245
REG_UPDATE_2(OTG_CRC1_WINDOWB_X_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
250
REG_UPDATE_2(OTG_CRC1_WINDOWB_Y_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
320
REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
195
REG_UPDATE_2(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
247
REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
352
REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
150
REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
164
REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
185
REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
118
REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
153
REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
186
REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
153
REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
186
REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
216
REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
157
REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
214
REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
122
REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
159
REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
193
REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,