sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

792

REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

801

REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

811

REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

820

REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

774

REG_SET_6(DCP_SPATIAL_DITHER_CNTL, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

681

REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

690

REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

699

REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

707

REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1015

REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

675

REG_SET_6(DSCL_EASF_V_BF_CNTL, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

790

REG_SET_6(DSCL_EASF_H_BF_CNTL, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

960

REG_SET_6(ISHARP_MODE, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

712

REG_SET_6(DSCC_PPS_CONFIG16, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

720

REG_SET_6(DSCC_PPS_CONFIG17, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

728

REG_SET_6(DSCC_PPS_CONFIG18, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

736

REG_SET_6(DSCC_PPS_CONFIG19, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

744

REG_SET_6(DSCC_PPS_CONFIG20, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

752

REG_SET_6(DSCC_PPS_CONFIG21, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

760

REG_SET_6(DSCC_PPS_CONFIG22, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

333

REG_SET_6(DSCC_PPS_CONFIG16, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

341

REG_SET_6(DSCC_PPS_CONFIG17, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

349

REG_SET_6(DSCC_PPS_CONFIG18, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

357

REG_SET_6(DSCC_PPS_CONFIG19, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

365

REG_SET_6(DSCC_PPS_CONFIG20, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

373

REG_SET_6(DSCC_PPS_CONFIG21, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

381

REG_SET_6(DSCC_PPS_CONFIG22, 0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

233

REG_SET_6(DCHUBP_REQ_SIZE_CONFIG, 0,