sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

224

value = REG_SET_4(DC_I2C_DATA, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

106

REG_SET_4(AFMT_GENERIC_HDR, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

483

REG_SET_4(DP_MSA_TIMING_PARAM3, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1506

REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1513

REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1520

REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1527

REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1534

REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1541

REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1548

REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1555

REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

252

REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

135

REG_SET_4(reg_region_cur, 0,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

709

REG_SET_4(WBSCL_COEF_RAM_TAP_DATA, 0,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

92

REG_SET_4(reg_region_cur, 0,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

88

REG_SET_4(VPG_GENERIC_PACKET_DATA, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

446

REG_SET_4(DP_MSA_TIMING_PARAM3, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

824

REG_SET_4(AFMT_GENERIC_HDR, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

96

REG_SET_4(AFMT_GENERIC_HDR, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

170

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

180

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

190

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

200

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

247

REG_SET_4(AFMT_GENERIC_HDR, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

221

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

231

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

241

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

251

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

261

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

271

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

281

REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

687

REG_SET_4(DP_MSA_TIMING_PARAM3, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

264

REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

688

REG_SET_4(SCL_TAP_CONTROL, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

660

REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

667

REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

674

REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

681

REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

688

REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

695

REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

702

REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

709

REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

716

REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

723

REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

730

REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

737

REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

744

REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

751

REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

758

REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

765

REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

772

REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

810

REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

817

REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

824

REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

831

REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

838

REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

845

REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

852

REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

859

REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

866

REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

873

REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

880

REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

887

REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

894

REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

901

REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

908

REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

915

REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

922

REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1006

REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1013

REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1020

REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1027

REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1034

REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1072

REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1079

REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1086

REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1093

REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1100

REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1107

REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1114

REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1121

REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1128

REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1135

REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1142

REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1149

REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1156

REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1163

REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1170

REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1177

REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1184

REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

922

REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

929

REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

936

REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

943

REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

950

REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

957

REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

964

REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

971

REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

978

REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

985

REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

992

REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

999

REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1166

REG_SET_4(SCL_TAP_CONTROL, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

256

REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

701

REG_SET_4(DSCL_EASF_V_BF_FINAL_MAX_MIN, 0,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

806

REG_SET_4(DSCL_EASF_H_BF_FINAL_MAX_MIN, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

605

REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

618

REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

687

REG_SET_4(DSCC_PPS_CONFIG12, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

693

REG_SET_4(DSCC_PPS_CONFIG13, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

699

REG_SET_4(DSCC_PPS_CONFIG14, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

226

REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

239

REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

308

REG_SET_4(DSCC_PPS_CONFIG12, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

314

REG_SET_4(DSCC_PPS_CONFIG13, 0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

320

REG_SET_4(DSCC_PPS_CONFIG14, 0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

379

REG_SET_4(DP_SYM32_ENC_VID_MSA0, 0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

385

REG_SET_4(DP_SYM32_ENC_VID_MSA1, 0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

391

REG_SET_4(DP_SYM32_ENC_VID_MSA2, 0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

397

REG_SET_4(DP_SYM32_ENC_VID_MSA3, 0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

403

REG_SET_4(DP_SYM32_ENC_VID_MSA4, 0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

409

REG_SET_4(DP_SYM32_ENC_VID_MSA5, 0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

415

REG_SET_4(DP_SYM32_ENC_VID_MSA6, 0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

421

REG_SET_4(DP_SYM32_ENC_VID_MSA7, 0,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

427

REG_SET_4(DP_SYM32_ENC_VID_MSA8, 0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

580

REG_SET_4(DCN_EXPANSION_MODE, 0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

204

REG_SET_4(DCN_EXPANSION_MODE, 0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

74

REG_SET_4(DCN_EXPANSION_MODE, 0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

147

REG_SET_4(DCN_EXPANSION_MODE, 0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

228

REG_SET_4(DCN_EXPANSION_MODE, 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

516

REG_SET_4(SHAPER_RAMA_REGION_0_1[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

523

REG_SET_4(SHAPER_RAMA_REGION_2_3[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

530

REG_SET_4(SHAPER_RAMA_REGION_4_5[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

537

REG_SET_4(SHAPER_RAMA_REGION_6_7[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

544

REG_SET_4(SHAPER_RAMA_REGION_8_9[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

551

REG_SET_4(SHAPER_RAMA_REGION_10_11[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

558

REG_SET_4(SHAPER_RAMA_REGION_12_13[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

565

REG_SET_4(SHAPER_RAMA_REGION_14_15[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

573

REG_SET_4(SHAPER_RAMA_REGION_16_17[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

580

REG_SET_4(SHAPER_RAMA_REGION_18_19[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

587

REG_SET_4(SHAPER_RAMA_REGION_20_21[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

594

REG_SET_4(SHAPER_RAMA_REGION_22_23[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

601

REG_SET_4(SHAPER_RAMA_REGION_24_25[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

608

REG_SET_4(SHAPER_RAMA_REGION_26_27[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

615

REG_SET_4(SHAPER_RAMA_REGION_28_29[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

622

REG_SET_4(SHAPER_RAMA_REGION_30_31[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

629

REG_SET_4(SHAPER_RAMA_REGION_32_33[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

665

REG_SET_4(SHAPER_RAMB_REGION_0_1[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

672

REG_SET_4(SHAPER_RAMB_REGION_2_3[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

680

REG_SET_4(SHAPER_RAMB_REGION_4_5[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

687

REG_SET_4(SHAPER_RAMB_REGION_6_7[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

694

REG_SET_4(SHAPER_RAMB_REGION_8_9[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

701

REG_SET_4(SHAPER_RAMB_REGION_10_11[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

708

REG_SET_4(SHAPER_RAMB_REGION_12_13[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

715

REG_SET_4(SHAPER_RAMB_REGION_14_15[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

723

REG_SET_4(SHAPER_RAMB_REGION_16_17[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

730

REG_SET_4(SHAPER_RAMB_REGION_18_19[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

737

REG_SET_4(SHAPER_RAMB_REGION_20_21[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

744

REG_SET_4(SHAPER_RAMB_REGION_22_23[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

751

REG_SET_4(SHAPER_RAMB_REGION_24_25[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

758

REG_SET_4(SHAPER_RAMB_REGION_26_27[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

765

REG_SET_4(SHAPER_RAMB_REGION_28_29[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

772

REG_SET_4(SHAPER_RAMB_REGION_30_31[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

779

REG_SET_4(SHAPER_RAMB_REGION_32_33[rmu_idx], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

373

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

380

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

387

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

394

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

401

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

408

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

415

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

422

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

430

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

437

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

444

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

451

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

458

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

465

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

472

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

479

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

486

REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

525

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

532

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

540

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

547

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

554

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

561

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

568

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

575

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

583

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

590

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

597

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

604

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

611

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

618

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

625

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

632

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

639

REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1209

REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

806

REG_SET_4(OTG_TRIGA_CNTL, 0,

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

128

REG_SET_4(OPTC_DATA_SOURCE_SELECT, 0,