REG_READ
return REG_READ(MP1_SMN_C2PMSG_83);
res_val = REG_READ(MP1_SMN_C2PMSG_91);
dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT);
internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider
internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
return REG_READ(MP1_SMN_C2PMSG_83);
res_val = REG_READ(MP1_SMN_C2PMSG_91);
uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
*param_out = REG_READ(DAL_ARG_REG);
reg = REG_READ(DAL_RESP_REG);
*param_out = REG_READ(DAL_ARG_REG);
reg = REG_READ(DAL_RESP_REG);
return REG_READ(MP1_SMN_C2PMSG_83);
res_val = REG_READ(MP1_SMN_C2PMSG_91);
internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT);
internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL);
internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL); //dcf deep sleep divider
internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS);
internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT);
internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL);
internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT);
internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL);
internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT);
internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL);
return REG_READ(MP1_SMN_C2PMSG_83);
res_val = REG_READ(MP1_SMN_C2PMSG_91);
internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT);
internal->CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL);
internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);
internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
res_val = REG_READ(MP1_SMN_C2PMSG_91);
return REG_READ(MP1_SMN_C2PMSG_83);
res_val = REG_READ(MP1_SMN_C2PMSG_38);
return REG_READ(MP1_SMN_C2PMSG_37);
res_val = REG_READ(MP1_SMN_C2PMSG_91);
return REG_READ(MP1_SMN_C2PMSG_83);
dispclk_khz_reg = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK
dppclk_khz_reg = REG_READ(CLK1_CLK1_CURRENT_CNT); // DPPCLK
dprefclk_khz_reg = REG_READ(CLK1_CLK2_CURRENT_CNT); // DPREFCLK
dcfclk_khz_reg = REG_READ(CLK1_CLK3_CURRENT_CNT); // DCFCLK
dtbclk_khz_reg = REG_READ(CLK1_CLK4_CURRENT_CNT); // DTBCLK
fclk_khz_reg = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK
pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
reg = REG_READ(DAL_RESP_REG);
*param_out = REG_READ(DAL_ARG_REG);
reg = REG_READ(DAL_RESP_REG);
*param_out = REG_READ(DAL_ARG_REG);
actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT);
internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT);
internal->CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL);
internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);
internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
ssc_enable = REG_READ(CLK6_spll_field_8) & CLK6_spll_field_8__spll_ssc_en_MASK;
ssc_enable = REG_READ(CLK5_spll_field_8) & CLK5_spll_field_8__spll_ssc_en_MASK;
clock_source = REG_READ(CLK1_CLK2_BYPASS_CNTL) & CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK;
res_val = REG_READ(MP1_SMN_C2PMSG_91);
return REG_READ(MP1_SMN_C2PMSG_83);
pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
fclk_did = REG_READ(CLK2_CLK2_DFS_CNTL);
*param_out = REG_READ(DAL_ARG_REG);
reg = REG_READ(DAL_RESP_REG);
*param_out = REG_READ(DAL_ARG_REG);
reg = REG_READ(DAL_RESP_REG);
uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);
s2 = REG_READ(BIOS_SCRATCH_2);
unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);
value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
uint32_t value = REG_READ(AUX_ARB_CONTROL);
value = REG_READ(AUX_CONTROL);
value = REG_READ(AUX_ARB_CONTROL);
value = REG_READ(AUX_SW_STATUS);
uint32_t value = REG_READ(AUX_ARB_CONTROL);
clock_hz = REG_READ(PHASE[inst]);
modulo_hz = REG_READ(MODULO[inst]);
*state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA);
dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);
dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);
dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
REG_READ(DMCU_IRAM_RD_DATA));
dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15);
*state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA);
*cmd = REG_READ(SLAVE_COMM_CMD_REG);
*data1 = REG_READ(SLAVE_COMM_DATA_REG1);
*data2 = REG_READ(SLAVE_COMM_DATA_REG2);
*data3 = REG_READ(SLAVE_COMM_DATA_REG3);
REG_READ(DP_MSE_SAT_UPDATE);
value = REG_READ(DP_DPHY_INTERNAL_CTRL);
REG_READ(BL_PWM_CNTL);
REG_READ(BL_PWM_CNTL2);
REG_READ(BL_PWM_PERIOD_CNTL);
value = REG_READ(BIOS_SCRATCH_2);
REG_READ(BL_PWM_CNTL);
REG_READ(BL_PWM_CNTL2);
REG_READ(BL_PWM_PERIOD_CNTL);
REG_READ(BL_PWM_PERIOD_CNTL);
REG_READ(BL_PWM_CNTL);
value = REG_READ(DP_SEC_CNTL);
misc1 = REG_READ(DP_MSA_MISC);
value = REG_READ(DP_SEC_CNTL);
value = REG_READ(DP_SEC_CNTL);
REG_READ(AFMT_VBI_PACKET_CONTROL);
power_ctl = REG_READ(DCFE_MEM_PWR_CTRL);
unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);
uint32_t wbscl_mode = REG_READ(WBSCL_MODE);
REG_READ(BL_PWM_CNTL);
REG_READ(BL_PWM_CNTL2);
REG_READ(BL_PWM_PERIOD_CNTL);
REG_READ(BL_PWM_CNTL);
REG_READ(BL_PWM_CNTL2);
REG_READ(BL_PWM_PERIOD_CNTL);
REG_READ(DP_MSE_SAT_UPDATE);
value = REG_READ(DP_DPHY_INTERNAL_CTRL);
value = REG_READ(DP_SEC_CNTL);
misc1 = REG_READ(DP_MSA_MISC);
value = REG_READ(DP_SEC_CNTL);
value = REG_READ(DP_SEC_CNTL);
value = REG_READ(DP_SEC_CNTL);
value = REG_READ(DP_SEC_CNTL);
misc1 = REG_READ(DP_MSA_MISC);
s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
uint32_t scl_mode = REG_READ(SCL_MODE);
uint32_t scl_mode = REG_READ(SCL_MODE);
debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_MSB);
hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_LSB);
hubbub_state->test_debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
hubbub_state->watermark_change_cntl = REG_READ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL);
hubbub_state->dram_state_cntl = REG_READ(DCHUBBUB_ARB_DRAM_STATE_CNTL);
prog_wm_value = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A);
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A);
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A);
reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);
reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A);
value = REG_READ(HUBPREQ_DEBUG_DB);
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
uint32_t reg_val = REG_READ(DCHUBP_CNTL);
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
s->hubp_cntl = REG_READ(DCHUBP_CNTL);
s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
uint32_t reg_val = REG_READ(DCHUBP_CNTL);
s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);
s->hubp_cntl = REG_READ(DCHUBP_CNTL);
s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
reg_val = REG_READ(DCHUBP_CNTL);
s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);
s->hubp_cntl = REG_READ(DCHUBP_CNTL);
s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
uint32_t fb_base = REG_READ(MC_VM_FB_LOCATION_BASE);
uint32_t fb_top = REG_READ(MC_VM_FB_LOCATION_TOP);
uint32_t fb_offset = REG_READ(MC_VM_FB_OFFSET);
value = REG_READ(MICROSECOND_TIME_BASE_DIV);
s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);
s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);
s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);
s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);
uint32_t value = REG_READ(CC_DC_PIPE_DIS);
uint32_t value = REG_READ(CC_DC_PIPE_DIS);
uint32_t value = REG_READ(CC_DC_PIPE_DIS);
uint32_t value = REG_READ(CC_DC_PIPE_DIS);
uint32_t value = REG_READ(CC_DC_PIPE_DIS);
uint32_t value = REG_READ(CC_DC_PIPE_DIS);
return REG_READ(DMCUB_INBOX1_WPTR);
return REG_READ(DMCUB_INBOX1_RPTR);
return REG_READ(DMCUB_OUTBOX1_WPTR);
return REG_READ(DMCUB_OUTBOX0_WPTR);
test.all = REG_READ(DMCUB_GPINT_DATAIN1);
return REG_READ(DMCUB_SCRATCH7);
status.all = REG_READ(DMCUB_SCRATCH0);
boot_options.all = REG_READ(DMCUB_SCRATCH14);
return REG_READ(DMCUB_TIMER_CURRENT);
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
scratch = REG_READ(DMCUB_SCRATCH7);
return REG_READ(DMCUB_INBOX1_WPTR);
return REG_READ(DMCUB_INBOX1_RPTR);
return REG_READ(DMCUB_OUTBOX1_WPTR);
status.all = REG_READ(DMCUB_SCRATCH0);
test.all = REG_READ(DMCUB_GPINT_DATAIN1);
return REG_READ(DMCUB_SCRATCH7);
uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
status.all = REG_READ(DMCUB_SCRATCH0);
option.all = REG_READ(DMCUB_SCRATCH14);
boot_options.all = REG_READ(DMCUB_SCRATCH14);
return REG_READ(DMCUB_OUTBOX0_WPTR);
return REG_READ(DMCUB_TIMER_CURRENT);
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);
scratch = REG_READ(DMCUB_SCRATCH7);
return REG_READ(DMCUB_INBOX1_WPTR);
return REG_READ(DMCUB_INBOX1_RPTR);
return REG_READ(DMCUB_OUTBOX1_WPTR);
status.all = REG_READ(DMCUB_SCRATCH0);
test.all = REG_READ(DMCUB_GPINT_DATAIN1);
return REG_READ(DMCUB_SCRATCH7);
uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
status.all = REG_READ(DMCUB_SCRATCH0);
boot_options.all = REG_READ(DMCUB_SCRATCH14);
return REG_READ(DMCUB_OUTBOX0_WPTR);
return REG_READ(DMCUB_TIMER_CURRENT);
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
return REG_READ(DMCUB_SCRATCH17);
index = REG_READ(DMCUB_SCRATCH15);
index = REG_READ(DMCUB_SCRATCH23);
scratch = REG_READ(DMCUB_SCRATCH7);
return REG_READ(DMCUB_INBOX1_WPTR);
return REG_READ(DMCUB_INBOX1_RPTR);
return REG_READ(DMCUB_OUTBOX1_WPTR);
status.all = REG_READ(DMCUB_SCRATCH0);
test.all = REG_READ(DMCUB_GPINT_DATAIN1);
return REG_READ(DMCUB_SCRATCH7);
uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
status.all = REG_READ(DMCUB_SCRATCH0);
option.all = REG_READ(DMCUB_SCRATCH14);
boot_options.all = REG_READ(DMCUB_SCRATCH14);
return REG_READ(DMCUB_OUTBOX0_WPTR);
return REG_READ(DMCUB_TIMER_CURRENT);
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);
return REG_READ(DMCUB_SCRATCH17);
status.all = REG_READ(DMCUB_SCRATCH0);
return REG_READ(DMCUB_INBOX1_WPTR);
return REG_READ(DMCUB_INBOX1_RPTR);
return REG_READ(DMCUB_OUTBOX1_WPTR);
status.all = REG_READ(DMCUB_SCRATCH0);
test.all = REG_READ(DMCUB_GPINT_DATAIN1);
return REG_READ(DMCUB_SCRATCH7);
uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
status.all = REG_READ(DMCUB_SCRATCH0);
boot_options.all = REG_READ(DMCUB_SCRATCH14);
return REG_READ(DMCUB_OUTBOX0_WPTR);
return REG_READ(DMCUB_TIMER_CURRENT);
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
return REG_READ(DMCUB_SCRATCH17);
dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP);
dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0);
dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1);
dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2);
dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3);
dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4);
dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5);
dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6);
dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7);
dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8);
dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9);
dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10);
dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11);
dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12);
dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13);
dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14);
*msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0);