sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

84

regval = REG_GET_3(gpio.MASK_reg,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

702

REG_GET_3(DP_SYM32_ENC_VID_PIXEL_FORMAT,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1022

REG_GET_3(DCN_SURF0_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1031

REG_GET_3(DCN_SURF1_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1064

REG_GET_3(DCHUBP_CNTL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1253

REG_GET_3(DCN_SURF0_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1262

REG_GET_3(DCN_SURF1_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1295

REG_GET_3(DCHUBP_CNTL,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1600

REG_GET_3(DCN_SURF0_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1604

REG_GET_3(DCN_SURF1_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1608

REG_GET_3(DCN_CUR0_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

491

REG_GET_3(DCN_SURF0_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

495

REG_GET_3(DCN_SURF1_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

499

REG_GET_3(DCN_CUR0_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

945

REG_GET_3(DCN_SURF0_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

954

REG_GET_3(DCN_SURF1_TTU_CNTL0,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

987

REG_GET_3(DCHUBP_CNTL,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

494

REG_GET_3(MPCC_STATUS[mpcc_id],

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

228

REG_GET_3(OPTC_DATA_SOURCE_SELECT,