Symbol: REG_GET_2
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
85
REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel);
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
72
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
77
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
82
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
87
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
72
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
77
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
82
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
87
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1228
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1233
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1238
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1243
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1977
REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, &fe_clk_en[0],
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1980
REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, &fe_clk_en[1],
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1983
REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, &fe_clk_en[2],
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1986
REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, &fe_clk_en[3],
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1989
REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, &fe_clk_en[4],
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
565
REG_GET_2(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, &src_sel, SYMCLK32_SE3_EN, &en);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
792
REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, &src_sel, SYMCLKA_FE_EN, &en);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
795
REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, &src_sel, SYMCLKB_FE_EN, &en);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
798
REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, &src_sel, SYMCLKC_FE_EN, &en);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
801
REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, &src_sel, SYMCLKD_FE_EN, &en);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
804
REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, &src_sel, SYMCLKE_FE_EN, &en);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
888
REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
893
REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
898
REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
903
REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
130
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
135
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
140
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
145
REG_GET_2(OTG_PIXEL_RATE_DIV,
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
477
REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
271
REG_GET_2(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, &ref_base_div,
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
152
REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, &blon, LVTMA_BLON_OVRD, &blon_ovrd);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
168
REG_GET_2(PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
205
REG_GET_2(BL_PWM_PERIOD_CNTL,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
74
REG_GET_2(cur_csc_reg,
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
59
REG_GET_2(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value1,
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
175
REG_GET_2(PWRSEQ_CNTL, PANEL_DIGON, &dig_on, PANEL_DIGON_OVRD, &dig_on_ovrd);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1523
REG_GET_2(DP_PIXEL_FORMAT,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
66
REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
976
REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
53
REG_GET_2(PRE_DEGAM,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
154
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
229
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
95
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
107
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
148
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
153
REG_GET_2(DWB_OGAM_CONTROL,
sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c
113
REG_GET_2(gpio.MASK_reg,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
467
REG_GET_2(DP_DPHY_SYM32_SAT_VC0,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
470
REG_GET_2(DP_DPHY_SYM32_SAT_VC1,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
473
REG_GET_2(DP_DPHY_SYM32_SAT_VC2,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
476
REG_GET_2(DP_DPHY_SYM32_SAT_VC3,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
480
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL0,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
483
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL1,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
486
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL2,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
489
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL3,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
568
REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
447
REG_GET_2(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, &curr_det_sizes[0],
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
450
REG_GET_2(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, &curr_det_sizes[1],
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
453
REG_GET_2(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, &curr_det_sizes[2],
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
456
REG_GET_2(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, &curr_det_sizes[3],
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
951
REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
983
REG_GET_2(DCHUBBUB_ARB_MALL_CNTL, MALL_IN_USE, &mall_en,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
267
REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1011
REG_GET_2(DCN_TTU_QOS_WM,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1015
REG_GET_2(DCN_GLOBAL_TTU_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1050
REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1054
REG_GET_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1075
REG_GET_2(DCN_TTU_QOS_WM,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
924
REG_GET_2(BLANK_OFFSET_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
934
REG_GET_2(DST_AFTER_SCALER,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
939
REG_GET_2(PREFETCH_SETTINS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
943
REG_GET_2(PREFETCH_SETTINGS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
947
REG_GET_2(VBLANK_PARAMETERS_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
975
REG_GET_2(PER_LINE_DELIVERY_PRE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
979
REG_GET_2(PER_LINE_DELIVERY,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1155
REG_GET_2(BLANK_OFFSET_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1165
REG_GET_2(DST_AFTER_SCALER,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1170
REG_GET_2(PREFETCH_SETTINS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1174
REG_GET_2(PREFETCH_SETTINGS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1178
REG_GET_2(VBLANK_PARAMETERS_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1206
REG_GET_2(PER_LINE_DELIVERY_PRE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1210
REG_GET_2(PER_LINE_DELIVERY,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1242
REG_GET_2(DCN_TTU_QOS_WM,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1246
REG_GET_2(DCN_GLOBAL_TTU_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1281
REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1285
REG_GET_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1306
REG_GET_2(DCN_TTU_QOS_WM,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1466
REG_GET_2(BLANK_OFFSET_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1473
REG_GET_2(DST_AFTER_SCALER,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1514
REG_GET_2(PER_LINE_DELIVERY,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1517
REG_GET_2(PER_LINE_DELIVERY_PRE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1587
REG_GET_2(DCN_TTU_QOS_WM,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
357
REG_GET_2(BLANK_OFFSET_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
364
REG_GET_2(DST_AFTER_SCALER,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
405
REG_GET_2(PER_LINE_DELIVERY,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
408
REG_GET_2(PER_LINE_DELIVERY_PRE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
478
REG_GET_2(DCN_TTU_QOS_WM,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
860
REG_GET_2(BLANK_OFFSET_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
870
REG_GET_2(DST_AFTER_SCALER,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
874
REG_GET_2(PREFETCH_SETTINGS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
878
REG_GET_2(VBLANK_PARAMETERS_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
904
REG_GET_2(PER_LINE_DELIVERY_PRE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
908
REG_GET_2(PER_LINE_DELIVERY,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
934
REG_GET_2(DCN_TTU_QOS_WM,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
938
REG_GET_2(DCN_GLOBAL_TTU_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
973
REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
977
REG_GET_2(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
998
REG_GET_2(DCN_TTU_QOS_WM,
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
154
REG_GET_2(MPCC_STATUS[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
456
REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
557
REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
140
REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], MPCC_OGAM_MODE_CURRENT, &state_mode,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1486
REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1512
REG_GET_2(MPCC_OGAM_CONTROL[mpcc_inst],
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
330
REG_GET_2(DPG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1239
REG_GET_2(OTG_V_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1339
REG_GET_2(OTG_V_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1361
REG_GET_2(OTG_V_SYNC_A,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1365
REG_GET_2(OTG_H_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1369
REG_GET_2(OTG_H_SYNC_A,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1416
REG_GET_2(OTG_V_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1420
REG_GET_2(OTG_H_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1575
REG_GET_2(OTG_CRC0_DATA_RG,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1585
REG_GET_2(OTG_CRC1_DATA_RG,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
475
REG_GET_2(OTG_BLANK_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
702
REG_GET_2(OTG_STATUS_POSITION,
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
307
REG_GET_2(OTG_PIPE_UPDATE_STATUS,
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
73
REG_GET_2(OTG_V_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
76
REG_GET_2(OTG_H_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
256
REG_GET_2(OTG_V_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
278
REG_GET_2(OTG_V_SYNC_A,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
282
REG_GET_2(OTG_H_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
286
REG_GET_2(OTG_H_SYNC_A,
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
448
REG_GET_2(CC_DC_HDMI_STRAPS,
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
495
REG_GET_2(CC_DC_HDMI_STRAPS,
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
475
REG_GET_2(CC_DC_HDMI_STRAPS,
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
481
REG_GET_2(CC_DC_HDMI_STRAPS,
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
487
REG_GET_2(CC_DC_HDMI_STRAPS,