sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c
61
REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
138
REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
143
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
147
REG_GET(DENTIST_DISPCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
433
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
434
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
206
REG_GET(CLK4_CLK_PLL_REQ, FbMult_int, &clk_mgr->base.dentist_vco_freq_khz);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
266
REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
267
REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
198
REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
199
REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
272
REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
273
REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
242
REG_GET(CLK6_0_CLK6_spll_field_8, spll_ssc_en, &ssc_enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
421
REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
422
REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
902
REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
366
REG_GET(DENTIST_DISPCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
415
REG_GET(DENTIST_DISPCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
462
REG_GET(DENTIST_DISPCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
480
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
547
REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
548
REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1489
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
631
REG_GET(DENTIST_DISPCLK_CNTL,
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
54
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value);
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
51
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1113
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value);
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
854
REG_GET(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
858
REG_GET(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
862
REG_GET(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
866
REG_GET(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
870
REG_GET(DCCG_GATE_DISABLE_CNTL5,
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
289
*sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
305
REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
323
REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
157
REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
162
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
487
REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
286
REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
121
REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
133
REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
137
REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
148
REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
299
REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
311
REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
395
REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
401
REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
415
REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
74
REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1607
REG_GET(DP_MSE_SAT_UPDATE,
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1610
REG_GET(DP_MSE_SAT_UPDATE,
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1630
REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
241
REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
685
REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
754
dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
791
dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
848
REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending);
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
586
REG_GET(CONTROL,
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
119
REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
153
REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
166
REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
184
REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
58
REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
59
REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
62
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
63
REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
99
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1510
REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
914
REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1432
REG_GET(DCFE_MEM_PWR_STATUS,
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1440
REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
177
REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
204
REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
205
REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c
61
REG_GET(PAGE_TABLE_BASE_ADDR_LO32,
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
73
REG_GET(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value);
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
211
REG_GET(RDPCSTX_PHY_CNTL6,
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
223
REG_GET(RDPCSTX_PHY_CNTL6,
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
106
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
134
REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
163
REG_GET(PWRSEQ_CNTL, PANEL_BLON, &value);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
173
REG_GET(PWRSEQ_STATE, PANEL_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
191
REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
57
REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
58
REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
60
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &bl_pwm);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
61
REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c
68
REG_GET(VPG_MEM_PWR, VPG_GSP_MEM_PWR_STATE, &vpg_gsp_mem_pwr_state);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1331
REG_GET(DP_MSE_SAT_UPDATE,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1334
REG_GET(DP_MSE_SAT_UPDATE,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1354
REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1435
REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
453
REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
537
REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1504
REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
918
REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
193
REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
205
REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
206
REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
207
REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
208
REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
278
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
293
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
356
REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
358
REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
359
REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
361
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
362
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
364
REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
365
REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
452
REG_GET(DP_SEC_METADATA_TRANSMISSION,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
587
REG_GET(DIG_FIFO_STATUS,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
392
REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
394
REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
395
REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
397
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
398
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
400
REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
401
REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
511
REG_GET(DP_SEC_METADATA_TRANSMISSION,
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
615
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
625
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
628
REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
666
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
672
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
675
REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
410
REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
412
REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
414
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
415
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
417
REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
418
REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
59
REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
91
REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &reset_val);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
372
REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
374
REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
376
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
377
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
379
REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
380
REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
401
REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
61
REG_GET(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, &enabled);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
71
REG_GET(DIG_BE_CLK_CNTL, DIG_BE_MODE, &value);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
386
REG_GET(DIG_FE_CLK_CNTL, DIG_FE_SYMCLK_FE_G_CLOCK_ON, &is_symclk_on);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
399
REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &reset_val);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
430
REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, &value);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
163
REG_GET(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, &clk_enabled);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
164
REG_GET(DIG_BE_EN_CNTL, DIG_BE_ENABLE, &dig_enabled);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
173
REG_GET(DIG_BE_CLK_CNTL, DIG_BE_MODE, &value);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
384
REG_GET(DP_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, &s->dsc_mode);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
387
REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
389
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
390
REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
392
REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
393
REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
101
REG_GET(CM_IGAM_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
103
REG_GET(CM_IGAM_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
105
REG_GET(CM_DGAM_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
107
REG_GET(CM_RGAM_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
109
REG_GET(CM_GAMUT_REMAP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
99
REG_GET(DPP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
191
REG_GET(CM_GAMUT_REMAP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
272
REG_GET(CM_TEST_DEBUG_DATA,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
530
REG_GET(CM_TEST_DEBUG_DATA,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
710
REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
802
REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
872
REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num);
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
56
REG_GET(DPP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
60
REG_GET(CM_DGAM_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
64
REG_GET(CM_SHAPER_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
69
REG_GET(CM_3DLUT_MODE,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
73
REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
502
REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, &state_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
595
REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, &state_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
72
REG_GET(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
999
REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1242
REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1244
REG_GET(CM_3DLUT_MODE,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
126
REG_GET(CM_POST_CSC_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1266
REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
49
REG_GET(DPP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
531
REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
540
REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
549
REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
558
REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
58
REG_GET(CM_GAMCOR_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
61
REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &gamcor_lut_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
68
REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, &s->shaper_lut_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
70
REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &s->lut3d_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
72
REG_GET(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
74
REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &s->lut3d_size);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
758
REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &mode_current);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
759
REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &in_use);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
78
REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &s->rgam_lut_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
80
REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
857
REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &state_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
395
REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &gamut_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
417
REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &selection);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
64
REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &state_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
67
REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &lut_mode);
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
49
REG_GET(DPP_CONTROL,
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
191
REG_GET(CUR0_MATRIX_MODE, CUR0_MATRIX_MODE_CURRENT, &mode_select);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
146
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
147
REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
148
REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
149
REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
150
REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
151
REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
152
REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
153
REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
228
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
251
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
94
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
100
REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
101
REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
102
REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
103
REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
104
REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
105
REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
106
REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
147
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
170
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
99
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
138
REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &pre_locked);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
166
REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &pre_locked);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
199
REG_GET(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, &dwb_enabled);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
200
REG_GET(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, &fc_frame_capture_en);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
376
REG_GET(DWB_GAMUT_REMAP_MODE, DWB_GAMUT_REMAP_MODE_CURRENT, ¤t_mode);
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
45
REG_GET(MASK_reg, MASK, &gpio->store.mask);
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
46
REG_GET(A_reg, A, &gpio->store.a);
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
47
REG_GET(EN_reg, EN, &gpio->store.en);
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
86
REG_GET(Y_reg, Y, value);
sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c
76
REG_GET(int_status,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
448
REG_GET(RDPCSTX_PHY_CNTL6[enc->transmitter], RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
460
REG_GET(DP_DPHY_SYM32_STATUS,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
462
REG_GET(DP_DPHY_SYM32_CONTROL,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
464
REG_GET(DP_DPHY_SYM32_CONTROL,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
57
REG_GET(DP_DPHY_SYM32_STATUS,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
498
REG_GET(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
540
REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp0_enabled);
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
541
REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp2_enabled);
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
542
REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp3_enabled);
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
543
REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL11, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp11_enabled);
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
695
REG_GET(DP_SYM32_ENC_CONTROL,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
697
REG_GET(DP_SYM32_ENC_VID_STREAM_CONTROL,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
699
REG_GET(DP_STREAM_ENC_INPUT_MUX_CONTROL,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
707
REG_GET(DP_SYM32_ENC_SDP_CONTROL,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
712
REG_GET(DP_STREAM_MAPPER_CONTROL0,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
716
REG_GET(DP_STREAM_MAPPER_CONTROL1,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
720
REG_GET(DP_STREAM_MAPPER_CONTROL2,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
724
REG_GET(DP_STREAM_MAPPER_CONTROL3,
sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c
53
REG_GET(RDPCSTX_PHY_CNTL6[enc->transmitter], RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
109
REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
641
REG_GET(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, &hubbub_state->vm_error_mode);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
644
REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, &hubbub_state->vm_error_status);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
645
REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, &hubbub_state->vm_error_vmid);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
646
REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, &hubbub_state->vm_error_pipe);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
628
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
631
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
634
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
637
REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
642
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
645
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
648
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
651
REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
656
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
659
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
662
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
665
REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
670
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
673
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
676
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
679
REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
78
REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
466
REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
151
ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
55
REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
58
REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
61
REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
64
REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
67
REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
157
ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
55
REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
58
REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
61
REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
64
REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
67
REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
888
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
891
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
894
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
897
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
900
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
903
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
908
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
911
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
914
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
917
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
920
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
923
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
928
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
931
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
934
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
937
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
940
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
943
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
948
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
951
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
954
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
957
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
960
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
963
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
410
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
413
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
416
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
419
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
422
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
425
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
428
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
431
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
435
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
438
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
441
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
444
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
447
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
450
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
453
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
456
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
461
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
464
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
467
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
470
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
473
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
476
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
479
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
482
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
487
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
490
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
493
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
496
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
499
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
502
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
505
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
508
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
53
REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
56
REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
59
REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
62
REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
65
REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
91
ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1169
ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &cur_compbuf_size_seg) && !cur_compbuf_size_seg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1212
REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &temp);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
48
REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
51
REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
54
REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
562
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
565
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
568
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
57
REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
571
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
574
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
577
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
582
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
585
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
588
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
591
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
594
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
597
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
60
REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1001
REG_GET(NOM_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1004
REG_GET(NOM_PARAMETERS_6,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1007
REG_GET(NOM_PARAMETERS_7,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1027
REG_GET(DCN_SURF0_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1036
REG_GET(DCN_SURF1_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1041
REG_GET(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1044
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1047
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1058
REG_GET(DCSURF_TILING_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1061
REG_GET(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1069
REG_GET(HUBP_CLK_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1072
REG_GET(DCN_GLOBAL_TTU_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1079
REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1082
REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1085
REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1088
REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1318
REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
760
REG_GET(DCSURF_FLIP_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
763
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
766
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
899
REG_GET(HUBPRET_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
907
REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
910
REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
913
REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
916
REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
928
REG_GET(BLANK_OFFSET_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
931
REG_GET(DST_DIMENSIONS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
95
REG_GET(DCHUBP_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
951
REG_GET(REF_FREQ_TO_PIX_FREQ,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
955
REG_GET(VBLANK_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
958
REG_GET(VBLANK_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
962
REG_GET(NOM_PARAMETERS_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
966
REG_GET(NOM_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
969
REG_GET(NOM_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
972
REG_GET(NOM_PARAMETERS_5,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
984
REG_GET(PREFETCH_SETTINS_C,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
987
REG_GET(PREFETCH_SETTINGS_C,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
990
REG_GET(VBLANK_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
993
REG_GET(VBLANK_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
997
REG_GET(NOM_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1140
REG_GET(HUBPRET_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1148
REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1151
REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1159
REG_GET(BLANK_OFFSET_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1162
REG_GET(DST_DIMENSIONS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1182
REG_GET(REF_FREQ_TO_PIX_FREQ,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1186
REG_GET(VBLANK_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1189
REG_GET(VBLANK_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1193
REG_GET(NOM_PARAMETERS_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1197
REG_GET(NOM_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1200
REG_GET(NOM_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1203
REG_GET(NOM_PARAMETERS_5,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1215
REG_GET(PREFETCH_SETTINS_C,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1218
REG_GET(PREFETCH_SETTINGS_C,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1221
REG_GET(VBLANK_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1224
REG_GET(VBLANK_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1228
REG_GET(NOM_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1232
REG_GET(NOM_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1235
REG_GET(NOM_PARAMETERS_6,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1238
REG_GET(NOM_PARAMETERS_7,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1258
REG_GET(DCN_SURF0_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1267
REG_GET(DCN_SURF1_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1272
REG_GET(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1275
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1278
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1289
REG_GET(DCSURF_TILING_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1292
REG_GET(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1300
REG_GET(HUBP_CLK_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1303
REG_GET(DCN_GLOBAL_TTU_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1310
REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1313
REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1316
REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1319
REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1373
REG_GET(HUBPRET_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1469
REG_GET(BLANK_OFFSET_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1471
REG_GET(DST_DIMENSIONS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1476
REG_GET(REF_FREQ_TO_PIX_FREQ,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1502
REG_GET(VBLANK_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1505
REG_GET(NOM_PARAMETERS_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1508
REG_GET(NOM_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1510
REG_GET(NOM_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1512
REG_GET(NOM_PARAMETERS_5,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1520
REG_GET(VBLANK_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1523
REG_GET(NOM_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1526
REG_GET(NOM_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1528
REG_GET(NOM_PARAMETERS_6,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1530
REG_GET(NOM_PARAMETERS_7,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1532
REG_GET(VBLANK_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1534
REG_GET(VBLANK_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1612
REG_GET(FLIP_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1614
REG_GET(DCN_CUR0_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1616
REG_GET(DCN_CUR1_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1618
REG_GET(DCN_SURF0_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1620
REG_GET(DCN_SURF1_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
722
REG_GET(DMDATA_STATUS, DMDATA_DONE, &status);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
897
REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
911
REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
932
REG_GET(DCSURF_FLIP_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
935
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
938
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
106
REG_GET(FLIP_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
114
REG_GET(FLIP_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
267
REG_GET(HUBPRET_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
360
REG_GET(BLANK_OFFSET_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
362
REG_GET(DST_DIMENSIONS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
367
REG_GET(REF_FREQ_TO_PIX_FREQ,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
393
REG_GET(VBLANK_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
396
REG_GET(NOM_PARAMETERS_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
399
REG_GET(NOM_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
401
REG_GET(NOM_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
403
REG_GET(NOM_PARAMETERS_5,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
411
REG_GET(VBLANK_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
414
REG_GET(NOM_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
417
REG_GET(NOM_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
419
REG_GET(NOM_PARAMETERS_6,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
421
REG_GET(NOM_PARAMETERS_7,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
423
REG_GET(VBLANK_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
425
REG_GET(VBLANK_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
503
REG_GET(FLIP_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
505
REG_GET(DCN_CUR0_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
507
REG_GET(DCN_CUR1_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
509
REG_GET(DCN_SURF0_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
511
REG_GET(DCN_SURF1_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
558
REG_GET(VBLANK_PARAMETERS_5,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
560
REG_GET(VBLANK_PARAMETERS_6,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
562
REG_GET(FLIP_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
564
REG_GET(FLIP_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
566
REG_GET(FLIP_PARAMETERS_5,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
568
REG_GET(FLIP_PARAMETERS_6,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
570
REG_GET(FLIP_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
90
REG_GET(VBLANK_PARAMETERS_5,
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
98
REG_GET(VBLANK_PARAMETERS_6,
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
513
REG_GET(HUBPRET_READ_LINE_VALUE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
525
REG_GET(DCHUBP_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
76
REG_GET(DCHUBP_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
1002
REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
1005
REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
71
REG_GET(HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, &ret);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
725
REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
831
REG_GET(HUBPRET_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
853
REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
856
REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
864
REG_GET(BLANK_OFFSET_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
867
REG_GET(DST_DIMENSIONS,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
882
REG_GET(REF_FREQ_TO_PIX_FREQ,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
886
REG_GET(VBLANK_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
889
REG_GET(VBLANK_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
892
REG_GET(NOM_PARAMETERS_0,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
895
REG_GET(NOM_PARAMETERS_1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
898
REG_GET(NOM_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
901
REG_GET(NOM_PARAMETERS_5,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
912
REG_GET(PREFETCH_SETTINGS_C,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
915
REG_GET(VBLANK_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
918
REG_GET(VBLANK_PARAMETERS_4,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
921
REG_GET(NOM_PARAMETERS_2,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
924
REG_GET(NOM_PARAMETERS_3,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
927
REG_GET(NOM_PARAMETERS_6,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
930
REG_GET(NOM_PARAMETERS_7,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
950
REG_GET(DCN_SURF0_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
959
REG_GET(DCN_SURF1_TTU_CNTL1,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
964
REG_GET(DCSURF_SURFACE_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
967
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
970
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
981
REG_GET(DCSURF_TILING_CONFIG,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
984
REG_GET(DCSURF_SURFACE_CONTROL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
992
REG_GET(HUBP_CLK_CNTL,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
995
REG_GET(DCN_GLOBAL_TTU_CNTL,
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
255
REG_GET(MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, &pf_max_region);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2655
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2657
REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2660
REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2663
REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2681
REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2682
REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2684
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2686
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2689
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2691
REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2694
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2696
REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2699
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2701
REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
860
REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
861
REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
862
REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
863
REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1292
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
317
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
489
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
58
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
60
REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
171
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
299
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
355
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
458
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
242
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
303
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
143
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1489
REG_GET(DOMAIN16_PG_STATUS,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1494
REG_GET(DOMAIN17_PG_STATUS,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1498
REG_GET(DOMAIN18_PG_STATUS,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1502
REG_GET(DOMAIN19_PG_STATUS,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
85
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2659
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
49
#ifdef REG_GET
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
150
REG_GET(MPCC_TOP_SEL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
382
REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
409
REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
413
REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
414
REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
415
REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
429
REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
430
REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
449
REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
450
REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
451
REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
473
REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
302
REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], MPCC_OGAM_CONFIG_STATUS, &state_mode);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
477
REG_GET(MPCC_STATUS[id], MPCC_DISABLED, &mpc_disabled);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
491
REG_GET(MPCC_TOP_SEL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
550
REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
551
REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
552
REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
561
REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_inst],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1147
REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, &gamut_mode);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1168
REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, select);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1408
REG_GET(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, &status);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1410
REG_GET(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, &status);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1479
REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1480
REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1481
REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1490
REG_GET(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, &rmu_status);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1493
REG_GET(SHAPER_CONTROL[0],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1495
REG_GET(RMU_3DLUT_MODE[0],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1497
REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[0],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1499
REG_GET(RMU_3DLUT_MODE[0],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1502
REG_GET(SHAPER_CONTROL[1],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1504
REG_GET(RMU_3DLUT_MODE[1],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1506
REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[1],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1508
REG_GET(RMU_3DLUT_MODE[1],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
453
REG_GET(SHAPER_CONTROL[rmu_idx], MPC_RMU_SHAPER_LUT_MODE_CURRENT, &state_mode);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
84
REG_GET(DWB_MUX[dwb_id], MPC_DWB0_MUX_STATUS, &status);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
840
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, &power_status_shaper);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
841
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
850
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, &power_status_shaper);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
851
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
936
REG_GET(RMU_3DLUT_MODE[rmu_idx],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
939
REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[rmu_idx],
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
961
REG_GET(RMU_3DLUT_MODE[rmu_idx], MPC_RMU_3DLUT_SIZE, &lut_size);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
100
REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
102
REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
307
REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
701
REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
702
REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
763
REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
766
REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
788
REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
101
REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
435
REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
439
REG_GET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
443
REG_GET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
473
REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, mode_select);
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
495
REG_GET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
518
REG_GET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
76
REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
79
REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
334
REG_GET(DPG_STATUS,
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
347
REG_GET(DPG_CONTROL, DPG_EN, &dpg_en);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
349
REG_GET(DPG_STATUS, DPG_DOUBLE_BUFFER_PENDING, &double_buffer_pending);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1297
REG_GET(OTG_STEREO_STATUS,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1336
REG_GET(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1343
REG_GET(OTG_V_SYNC_A_CNTL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1346
REG_GET(OTG_V_TOTAL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1349
REG_GET(OTG_V_TOTAL_MAX,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1352
REG_GET(OTG_V_TOTAL_MIN,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1355
REG_GET(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1358
REG_GET(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1373
REG_GET(OTG_H_SYNC_A_CNTL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1376
REG_GET(OTG_H_TOTAL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1379
REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1382
REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1385
REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1388
REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1391
REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1410
REG_GET(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1448
REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1459
REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1566
REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1580
REG_GET(OTG_CRC0_DATA_B,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1590
REG_GET(OTG_CRC1_DATA_B,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
665
REG_GET(OTG_STATUS_FRAME_COUNT,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
706
REG_GET(OTG_NOM_VERT_POSITION,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
730
REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
733
REG_GET(OTG_VERT_SYNC_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
757
REG_GET(OTG_V_SYNC_A_CNTL,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
157
REG_GET(OPTC_DATA_FORMAT_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
281
REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total);
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
291
REG_GET(OTG_MASTER_UPDATE_LOCK,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
297
REG_GET(OTG_V_BLANK_START_END,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
299
REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total);
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
420
REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
422
REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
502
REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
126
REG_GET(OPTC_DATA_SOURCE_SELECT,
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
280
REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
293
REG_GET(OTG_DOUBLE_BUFFER_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
253
REG_GET(OTG_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
260
REG_GET(OTG_V_SYNC_A_CNTL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
263
REG_GET(OTG_V_TOTAL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
266
REG_GET(OTG_V_TOTAL_MAX,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
269
REG_GET(OTG_V_TOTAL_MIN,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
272
REG_GET(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
275
REG_GET(OTG_V_TOTAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
290
REG_GET(OTG_H_SYNC_A_CNTL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
293
REG_GET(OTG_H_TOTAL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
296
REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
299
REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
302
REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
305
REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
308
REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
311
REG_GET(INTERRUPT_DEST,
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
105
REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
443
REG_GET(OTG_CONTROL, OTG_MASTER_EN, &is_master_en);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
459
REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &lock_status);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
153
REG_GET(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
157
REG_GET(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
161
REG_GET(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
165
REG_GET(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
199
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
243
REG_GET(DOMAIN25_PG_STATUS,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
272
REG_GET(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
276
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
291
REG_GET(DOMAIN22_PG_STATUS,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
319
REG_GET(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
323
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
341
REG_GET(DOMAIN24_PG_STATUS,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
426
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
455
REG_GET(DOMAIN23_PG_STATUS,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
57
REG_GET(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
60
REG_GET(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
63
REG_GET(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
66
REG_GET(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
99
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
452
REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
499
REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
479
REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
485
REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
491
REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
100
REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
353
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
362
REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
462
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
465
REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
468
REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
471
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
474
REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
477
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
72
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
75
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
72
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
75
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
119
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
128
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
297
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
306
REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
467
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
470
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
473
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
476
REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
479
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
482
REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
485
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
68
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
71
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
89
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
121
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
327
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
336
REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
476
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
479
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
482
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
485
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
488
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
74
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
77
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
95
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
96
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
120
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
333
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
342
REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
506
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
509
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
512
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
515
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
518
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
563
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
73
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
76
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
94
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
95
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
313
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
322
REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
464
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
467
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
470
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
473
REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
476
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
479
REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
48
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
482
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
51
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
588
REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
652
REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
665
REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
71
REG_GET(DMCUB_CNTL,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
73
REG_GET(DMCUB_CNTL2,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
92
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
