REG_GENMASK8
disables = REG_GENMASK8(3, 0) >> lane_count;
disables = REG_GENMASK8(3, 0) << lane_count;
disables &= ~REG_GENMASK8(1, 0);
disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
#define C10_PLL0_ANA_FREQ_VCO_MASK REG_GENMASK8(7, 6)
#define C10_PLL1_DIV_MULTIPLIER_MASK REG_GENMASK8(7, 0)
#define C10_PLL2_MULTIPLIERL_MASK REG_GENMASK8(7, 0)
#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
#define C10_PLL9_FRACN_DENL_MASK REG_GENMASK8(7, 0)
#define C10_PLL10_FRACN_DENH_MASK REG_GENMASK8(7, 0)
#define C10_PLL11_FRACN_QUOT_L_MASK REG_GENMASK8(7, 0)
#define C10_PLL12_FRACN_QUOT_H_MASK REG_GENMASK8(7, 0)
#define C10_PLL13_FRACN_REM_L_MASK REG_GENMASK8(7, 0)
#define C10_PLL14_FRACN_REM_H_MASK REG_GENMASK8(7, 0)
#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
#define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3)
#define C10_PLL15_PIXELCLKDIV_MASK REG_GENMASK8(7, 6)
#define C10_PLL16_ANA_CPINT REG_GENMASK8(6, 0)
#define C10_PLL17_ANA_CPINTGS_H_MASK REG_GENMASK8(5, 0)
#define C10_PLL17_ANA_CPPROP_L_MASK REG_GENMASK8(7, 6)
#define C10_PLL18_ANA_CPPROP_H_MASK REG_GENMASK8(4, 0)
#define C10_PLL18_ANA_CPPROPGS_L_MASK REG_GENMASK8(7, 5)
#define C10_PLL19_ANA_CPPROPGS_H_MASK REG_GENMASK8(3, 0)
#define C10_PLL19_ANA_V2I_MASK REG_GENMASK8(5, 4)
#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
#define C10_TX1_TERMCTL_MASK REG_GENMASK8(7, 5)
#define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0)
#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)