Symbol: REG_FIELD_PREP8
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2974
disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
262
#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
266
#define C10_TX1_TERMCTL(val) REG_FIELD_PREP8(C10_TX1_TERMCTL_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
279
#define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
304
#define PHY_C20_CUSTOM_SERDES(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
307
#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
368
#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)