sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

111

#define IREF0RC_OFFSET(x) REG_FIELD_PREP(IREF0RC_OFFSET_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

117

#define IREF1RC_OFFSET(x) REG_FIELD_PREP(IREF1RC_OFFSET_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

149

#define GRC_CODE(x) REG_FIELD_PREP(GRC_CODE_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

151

#define GRC_CODE_FAST(x) REG_FIELD_PREP(GRC_CODE_FAST_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

153

#define GRC_CODE_SLOW(x) REG_FIELD_PREP(GRC_CODE_SLOW_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

155

#define GRC_CODE_NOM(x) REG_FIELD_PREP(GRC_CODE_NOM_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

216

#define MARGIN_000(x) REG_FIELD_PREP(MARGIN_000_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

218

#define UNIQ_TRANS_SCALE(x) REG_FIELD_PREP(UNIQ_TRANS_SCALE_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

248

#define DE_EMPHASIS(x) REG_FIELD_PREP(DE_EMPHASIS_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

48

#define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

50

#define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

69

#define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

72

#define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

75

#define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

80

#define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

82

#define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

84

#define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

87

#define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

90

#define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))

sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h

94

#define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

102

#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

104

#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

110

#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

19

#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

20

#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

21

#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

22

#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

23

#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

24

#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

25

#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

26

#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

27

#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

28

#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

29

#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

30

#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

31

#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

35

#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

60

#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

62

#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

67

#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

69

#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

78

#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

80

#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

95

#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

97

#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

225

#define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

226

#define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

227

#define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

237

#define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

238

#define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

239

#define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

240

#define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

241

#define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

247

#define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))

sys/dev/pci/drm/i915/display/icl_dsi_regs.h

102

#define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \

sys/dev/pci/drm/i915/display/icl_dsi_regs.h

34

#define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

64

#define AUD_CONFIG_N(n) (REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \

sys/dev/pci/drm/i915/display/intel_audio_regs.h

65

REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff))

sys/dev/pci/drm/i915/display/intel_audio_regs.h

67

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 0)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

68

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 1)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

69

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 2)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

70

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 3)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

71

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 4)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

72

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 5)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

73

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 6)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

74

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 7)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

75

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 8)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

76

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 9)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

77

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 10)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

78

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 11)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

79

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 12)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

80

#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 13)

sys/dev/pci/drm/i915/display/intel_cmtg_regs.h

13

#define CMTG_CLK_SEL_A_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)

sys/dev/pci/drm/i915/display/intel_cmtg_regs.h

15

#define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)

sys/dev/pci/drm/i915/display/intel_color.c

1828

return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 14)) |

sys/dev/pci/drm/i915/display/intel_color.c

1829

REG_FIELD_PREP(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, drm_color_lut_extract(color->blue, 14));

sys/dev/pci/drm/i915/display/intel_color.c

1834

return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_RED_UDW_MASK, drm_color_lut_extract(color->red, 14));

sys/dev/pci/drm/i915/display/intel_color.c

1862

return REG_FIELD_PREP(CGM_PIPE_GAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 10)) |

sys/dev/pci/drm/i915/display/intel_color.c

1863

REG_FIELD_PREP(CGM_PIPE_GAMMA_BLUE_LDW_MASK, drm_color_lut_extract(color->blue, 10));

sys/dev/pci/drm/i915/display/intel_color.c

1868

return REG_FIELD_PREP(CGM_PIPE_GAMMA_RED_UDW_MASK, drm_color_lut_extract(color->red, 10));

sys/dev/pci/drm/i915/display/intel_color.c

821

return REG_FIELD_PREP(PALETTE_RED_MASK, drm_color_lut_extract(color->red, 8)) |

sys/dev/pci/drm/i915/display/intel_color.c

822

REG_FIELD_PREP(PALETTE_GREEN_MASK, drm_color_lut_extract(color->green, 8)) |

sys/dev/pci/drm/i915/display/intel_color.c

823

REG_FIELD_PREP(PALETTE_BLUE_MASK, drm_color_lut_extract(color->blue, 8));

sys/dev/pci/drm/i915/display/intel_color.c

841

return REG_FIELD_PREP(PALETTE_RED_MASK, _i9xx_lut_10_ldw(color[0].red)) |

sys/dev/pci/drm/i915/display/intel_color.c

842

REG_FIELD_PREP(PALETTE_GREEN_MASK, _i9xx_lut_10_ldw(color[0].green)) |

sys/dev/pci/drm/i915/display/intel_color.c

843

REG_FIELD_PREP(PALETTE_BLUE_MASK, _i9xx_lut_10_ldw(color[0].blue));

sys/dev/pci/drm/i915/display/intel_color.c

869

return REG_FIELD_PREP(PALETTE_RED_MASK, _i9xx_lut_10_udw(color[0].red, color[1].red)) |

sys/dev/pci/drm/i915/display/intel_color.c

870

REG_FIELD_PREP(PALETTE_GREEN_MASK, _i9xx_lut_10_udw(color[0].green, color[1].green)) |

sys/dev/pci/drm/i915/display/intel_color.c

871

REG_FIELD_PREP(PALETTE_BLUE_MASK, _i9xx_lut_10_udw(color[0].blue, color[1].blue));

sys/dev/pci/drm/i915/display/intel_color.c

909

return REG_FIELD_PREP(PALETTE_RED_MASK, color->red & 0xff) |

sys/dev/pci/drm/i915/display/intel_color.c

910

REG_FIELD_PREP(PALETTE_GREEN_MASK, color->green & 0xff) |

sys/dev/pci/drm/i915/display/intel_color.c

911

REG_FIELD_PREP(PALETTE_BLUE_MASK, color->blue & 0xff);

sys/dev/pci/drm/i915/display/intel_color.c

917

return REG_FIELD_PREP(PALETTE_RED_MASK, color->red >> 8) |

sys/dev/pci/drm/i915/display/intel_color.c

918

REG_FIELD_PREP(PALETTE_GREEN_MASK, color->green >> 8) |

sys/dev/pci/drm/i915/display/intel_color.c

919

REG_FIELD_PREP(PALETTE_BLUE_MASK, color->blue >> 8);

sys/dev/pci/drm/i915/display/intel_color.c

940

return REG_FIELD_PREP(PREC_PALETTE_10_RED_MASK, drm_color_lut_extract(color->red, 10)) |

sys/dev/pci/drm/i915/display/intel_color.c

941

REG_FIELD_PREP(PREC_PALETTE_10_GREEN_MASK, drm_color_lut_extract(color->green, 10)) |

sys/dev/pci/drm/i915/display/intel_color.c

942

REG_FIELD_PREP(PREC_PALETTE_10_BLUE_MASK, drm_color_lut_extract(color->blue, 10));

sys/dev/pci/drm/i915/display/intel_color.c

955

return REG_FIELD_PREP(PREC_PALETTE_12P4_RED_LDW_MASK, color->red & 0x3f) |

sys/dev/pci/drm/i915/display/intel_color.c

956

REG_FIELD_PREP(PREC_PALETTE_12P4_GREEN_LDW_MASK, color->green & 0x3f) |

sys/dev/pci/drm/i915/display/intel_color.c

957

REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_LDW_MASK, color->blue & 0x3f);

sys/dev/pci/drm/i915/display/intel_color.c

963

return REG_FIELD_PREP(PREC_PALETTE_12P4_RED_UDW_MASK, color->red >> 6) |

sys/dev/pci/drm/i915/display/intel_color.c

964

REG_FIELD_PREP(PREC_PALETTE_12P4_GREEN_UDW_MASK, color->green >> 6) |

sys/dev/pci/drm/i915/display/intel_color.c

965

REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_UDW_MASK, color->blue >> 6);

sys/dev/pci/drm/i915/display/intel_color_regs.h

205

#define PAL_PREC_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_INDEX_VALUE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_color_regs.h

231

#define PRE_CSC_GAMC_INDEX_VALUE(x) REG_FIELD_PREP(PRE_CSC_GAMC_INDEX_VALUE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_color_regs.h

244

#define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_color_regs.h

78

#define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_color_regs.h

79

#define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_color_regs.h

80

#define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_color_regs.h

81

#define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */

sys/dev/pci/drm/i915/display/intel_color_regs.h

82

#define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

111

#define SWING_SEL_UPPER(x) REG_FIELD_PREP(SWING_SEL_UPPER_MASK, (x) >> 3)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

113

#define SWING_SEL_LOWER(x) REG_FIELD_PREP(SWING_SEL_LOWER_MASK, (x) & 0x7)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

115

#define FRC_LATENCY_OPTIM_VAL(x) REG_FIELD_PREP(FRC_LATENCY_OPTIM_MASK, (x))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

117

#define RCOMP_SCALAR(x) REG_FIELD_PREP(RCOMP_SCALAR_MASK, (x))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

124

#define POST_CURSOR_1(x) REG_FIELD_PREP(POST_CURSOR_1_MASK, (x))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

126

#define POST_CURSOR_2(x) REG_FIELD_PREP(POST_CURSOR_2_MASK, (x))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

128

#define CURSOR_COEFF(x) REG_FIELD_PREP(CURSOR_COEFF_MASK, (x))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

139

#define SCALING_MODE_SEL(x) REG_FIELD_PREP(SCALING_MODE_SEL_MASK, (x))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

141

#define RTERM_SELECT(x) REG_FIELD_PREP(RTERM_SELECT_MASK, (x))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

154

#define N_SCALAR(x) REG_FIELD_PREP(N_SCALAR_MASK, (x))

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

161

#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

35

#define PWR_UP_ALL_LANES REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x0)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

36

#define PWR_DOWN_LN_3_2_1 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xe)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

37

#define PWR_DOWN_LN_3_2 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xc)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

38

#define PWR_DOWN_LN_3 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x8)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

39

#define PWR_DOWN_LN_2_1_0 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x7)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

40

#define PWR_DOWN_LN_1_0 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x3)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

41

#define PWR_DOWN_LN_3_1 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xa)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

42

#define PWR_DOWN_LN_3_1_0 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xb)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

61

#define PROCESS_INFO_DOT_0 REG_FIELD_PREP(PROCESS_INFO_MASK, 0)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

62

#define PROCESS_INFO_DOT_1 REG_FIELD_PREP(PROCESS_INFO_MASK, 1)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

63

#define PROCESS_INFO_DOT_4 REG_FIELD_PREP(PROCESS_INFO_MASK, 2)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

65

#define VOLTAGE_INFO_0_85V REG_FIELD_PREP(VOLTAGE_INFO_MASK, 0)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

66

#define VOLTAGE_INFO_0_95V REG_FIELD_PREP(VOLTAGE_INFO_MASK, 1)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

67

#define VOLTAGE_INFO_1_05V REG_FIELD_PREP(VOLTAGE_INFO_MASK, 2)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

90

#define RUN_DCC_ONCE REG_FIELD_PREP(DCC_MODE_SELECT_MASK, 0)

sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h

93

#define LATENCY_OPTIM_VAL(x) REG_FIELD_PREP(LATENCY_OPTIM_MASK, (x))

sys/dev/pci/drm/i915/display/intel_crt_regs.h

16

#define ADPA_PIPE_SEL(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_crt_regs.h

18

#define ADPA_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK_CPT, (pipe))

sys/dev/pci/drm/i915/display/intel_crt_regs.h

20

#define ADPA_CRT_HOTPLUG_MONITOR_NONE REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 0)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

21

#define ADPA_CRT_HOTPLUG_MONITOR_COLOR REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 3)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

22

#define ADPA_CRT_HOTPLUG_MONITOR_MONO REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 2)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

25

#define ADPA_CRT_HOTPLUG_PERIOD_64 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 0)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

26

#define ADPA_CRT_HOTPLUG_PERIOD_128 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 1)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

28

#define ADPA_CRT_HOTPLUG_WARMUP_5MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 0)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

29

#define ADPA_CRT_HOTPLUG_WARMUP_10MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 1)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

31

#define ADPA_CRT_HOTPLUG_SAMPLE_2S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

32

#define ADPA_CRT_HOTPLUG_SAMPLE_4S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

34

#define ADPA_CRT_HOTPLUG_VOLTAGE_40 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

35

#define ADPA_CRT_HOTPLUG_VOLTAGE_50 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

36

#define ADPA_CRT_HOTPLUG_VOLTAGE_60 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

37

#define ADPA_CRT_HOTPLUG_VOLTAGE_70 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 3)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

39

#define ADPA_CRT_HOTPLUG_VOLREF_325MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 0)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

40

#define ADPA_CRT_HOTPLUG_VOLREF_475MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 1)

sys/dev/pci/drm/i915/display/intel_cursor.c

610

val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);

sys/dev/pci/drm/i915/display/intel_cursor.c

611

val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

103

#define CUR_BUF_END(end) REG_FIELD_PREP(CUR_BUF_END_MASK, (end))

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

105

#define CUR_BUF_START(start) REG_FIELD_PREP(CUR_BUF_START_MASK, (start))

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

17

#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

19

#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

20

#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

21

#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

22

#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

23

#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

26

#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

28

#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

50

#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

53

#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

61

#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

63

#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

69

#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

103

#define XELPDP_PORT_BUF_PORT_DATA_10BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

104

#define XELPDP_PORT_BUF_PORT_DATA_20BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

105

#define XELPDP_PORT_BUF_PORT_DATA_40BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

113

#define XELPDP_PORT_WIDTH(width) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

129

#define _XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

131

#define _XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

137

#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

149

#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

151

#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

173

#define XELPDP_PORT_MSGBUS_TIMER_VAL REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 0xa000)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

200

REG_FIELD_PREP(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

201

REG_FIELD_PREP(_XELPDP_DDI_CLOCK_SELECT_MASK, (val)))

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

223

#define TCSS_DISP_MAILBOX_IN_CMD_DATA(val) REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, val)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

259

#define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

260

#define C10_CMN0_REF_CLK_MPLLB_DIV REG_FIELD_PREP(REG_GENMASK(7, 5), 1)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

273

#define C10_VDR_CUSTOM_WIDTH_8_10 REG_FIELD_PREP(C10_VDR_CUSTOM_WIDTH_MASK, 0)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

50

#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

51

#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

52

#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

54

#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

57

#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

73

#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)

sys/dev/pci/drm/i915/display/intel_display.c

543

val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,

sys/dev/pci/drm/i915/display/intel_display_regs.h

1054

#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1055

#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1057

#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1058

#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1059

#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1061

#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1062

#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1065

#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1066

#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1068

#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1069

#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1070

#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1071

#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1073

#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1074

#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1076

#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */

sys/dev/pci/drm/i915/display/intel_display_regs.h

1077

#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */

sys/dev/pci/drm/i915/display/intel_display_regs.h

1085

#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1086

#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1087

#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1089

#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1091

#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1093

#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1095

#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1097

#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1109

#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1110

#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1111

#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1112

#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1114

#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1115

#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1116

#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1117

#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1128

#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1130

#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1141

#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1143

#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1172

#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1174

#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1451

#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1473

#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1502

#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1997

#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */

sys/dev/pci/drm/i915/display/intel_display_regs.h

1999

#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2000

#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */

sys/dev/pci/drm/i915/display/intel_display_regs.h

2001

#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2003

#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2004

#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2005

#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2006

#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2019

#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2020

#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2024

#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2025

#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2026

#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2027

#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2046

#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2241

#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2255

REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2264

#define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2280

#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2294

#define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2295

#define DP_TP_CTL_MODE_MST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2298

#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2299

#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2300

#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2304

#define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2305

#define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2306

#define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2307

#define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2308

#define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2309

#define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2337

#define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2339

#define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2341

#define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2342

#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2343

#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2346

#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2352

#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2427

#define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2428

#define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2429

#define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2430

#define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2431

#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2432

#define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2433

#define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2434

#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2439

#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2440

#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2441

#define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2442

#define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2443

#define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2444

#define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2471

#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2499

#define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2500

#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2501

#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2502

#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2504

#define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2505

#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2507

#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2508

#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2509

#define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2510

#define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2525

#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2527

#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2749

#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2821

#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2823

#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

350

#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))

sys/dev/pci/drm/i915/display/intel_display_regs.h

352

#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))

sys/dev/pci/drm/i915/display/intel_display_regs.h

358

#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))

sys/dev/pci/drm/i915/display/intel_display_regs.h

360

#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))

sys/dev/pci/drm/i915/display/intel_display_regs.h

366

#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))

sys/dev/pci/drm/i915/display/intel_display_regs.h

368

#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))

sys/dev/pci/drm/i915/display/intel_display_regs.h

374

#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))

sys/dev/pci/drm/i915/display/intel_display_regs.h

376

#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))

sys/dev/pci/drm/i915/display/intel_display_regs.h

382

#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))

sys/dev/pci/drm/i915/display/intel_display_regs.h

384

#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))

sys/dev/pci/drm/i915/display/intel_display_regs.h

390

#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))

sys/dev/pci/drm/i915/display/intel_display_regs.h

392

#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))

sys/dev/pci/drm/i915/display/intel_display_regs.h

398

#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/intel_display_regs.h

400

#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/intel_display_regs.h

637

#define DP_PIPE_SEL(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_display_regs.h

639

#define DP_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_IVB, (pipe))

sys/dev/pci/drm/i915/display/intel_display_regs.h

642

#define DP_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_CHV, (pipe))

sys/dev/pci/drm/i915/display/intel_display_regs.h

644

#define DP_LINK_TRAIN_PAT_1 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

645

#define DP_LINK_TRAIN_PAT_2 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

646

#define DP_LINK_TRAIN_PAT_IDLE REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

647

#define DP_LINK_TRAIN_OFF REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

649

#define DP_LINK_TRAIN_PAT_1_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

650

#define DP_LINK_TRAIN_PAT_2_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

651

#define DP_LINK_TRAIN_PAT_IDLE_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

652

#define DP_LINK_TRAIN_OFF_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

654

#define DP_VOLTAGE_0_4 REG_FIELD_PREP(DP_VOLTAGE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

655

#define DP_VOLTAGE_0_6 REG_FIELD_PREP(DP_VOLTAGE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

656

#define DP_VOLTAGE_0_8 REG_FIELD_PREP(DP_VOLTAGE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

657

#define DP_VOLTAGE_1_2 REG_FIELD_PREP(DP_VOLTAGE_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

659

#define DP_PRE_EMPHASIS_0 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

660

#define DP_PRE_EMPHASIS_3_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

661

#define DP_PRE_EMPHASIS_6 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

662

#define DP_PRE_EMPHASIS_9_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

664

#define DP_PORT_WIDTH(width) REG_FIELD_PREP(DP_PORT_WIDTH_MASK, (width) - 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

667

#define EDP_PLL_FREQ_270MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

668

#define EDP_PLL_FREQ_162MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

698

#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */

sys/dev/pci/drm/i915/display/intel_display_regs.h

737

#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */

sys/dev/pci/drm/i915/display/intel_display_regs.h

742

#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

743

#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

744

#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */

sys/dev/pci/drm/i915/display/intel_display_regs.h

745

#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */

sys/dev/pci/drm/i915/display/intel_display_regs.h

746

#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */

sys/dev/pci/drm/i915/display/intel_display_regs.h

748

#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

749

#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */

sys/dev/pci/drm/i915/display/intel_display_regs.h

750

#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */

sys/dev/pci/drm/i915/display/intel_display_regs.h

751

#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)

sys/dev/pci/drm/i915/display/intel_display_regs.h

752

#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */

sys/dev/pci/drm/i915/display/intel_display_regs.h

759

#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

760

#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

761

#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

762

#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */

sys/dev/pci/drm/i915/display/intel_display_regs.h

763

#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */

sys/dev/pci/drm/i915/display/intel_display_regs.h

766

#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))

sys/dev/pci/drm/i915/display/intel_display_regs.h

772

#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */

sys/dev/pci/drm/i915/display/intel_display_regs.h

773

#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */

sys/dev/pci/drm/i915/display/intel_display_regs.h

774

#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */

sys/dev/pci/drm/i915/display/intel_display_regs.h

777

#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

778

#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

779

#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

780

#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

783

#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

784

#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

785

#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

786

#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

865

#define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

866

#define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

867

#define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

868

#define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */

sys/dev/pci/drm/i915/display/intel_display_regs.h

871

#define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

872

#define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

873

#define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

874

#define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)

sys/dev/pci/drm/i915/display/intel_display_regs.h

880

#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)

sys/dev/pci/drm/i915/display/intel_display_regs.h

881

#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)

sys/dev/pci/drm/i915/display/intel_display_regs.h

883

#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))

sys/dev/pci/drm/i915/display/intel_display_regs.h

960

#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

961

#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

962

#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)

sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h

153

#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))

sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h

155

#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))

sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h

62

#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))

sys/dev/pci/drm/i915/display/intel_dmc.c

438

REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,

sys/dev/pci/drm/i915/display/intel_dmc.c

440

REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,

sys/dev/pci/drm/i915/display/intel_dmc.c

518

return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,

sys/dev/pci/drm/i915/display/intel_dmc.c

520

REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

307

#define PIPEDMC_INT_VECTOR_SCANLINE_COMP_ERROR REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0x1)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

308

#define PIPEDMC_INT_VECTOR_DC6V_FLIPQ_OVERLAP_ERROR REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0x2)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

309

#define PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0xff) /* Wa_16018781658:lnl[a0] */

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

330

#define PIPEDMC_FPQ_PLANEQ_3_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, (tail))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

332

#define PIPEDMC_FPQ_PLANEQ_2_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, (tail))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

334

#define PIPEDMC_FPQ_PLANEQ_1_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, (tail))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

336

#define PIPEDMC_FPQ_FASTQ_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_FASTQ_TP_MASK, (tail))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

338

#define PIPEDMC_FPQ_GENERALQ_TP(tail) REG_FIELD_PREP(PIPEDMC_FPQ_GENERALQ_TP_MASK, (tail))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

360

#define PIPEDMC_SCANLINE_LOWER(scanline) REG_FIELD_PREP(PIPEDMC_SCANLINE_LOWER_MASK, (scanline))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

366

#define PIPEDMC_SCANLINE_UPPER(scanline) REG_FIELD_PREP(PIPEDMC_SCANLINE_UPPER_MASK, (scanline))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

542

#define PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

544

#define PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

546

#define PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

548

#define PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

558

#define LNL_FQ_DSB_ID(dsb_id) REG_FIELD_PREP(LNL_FQ_DSB_ID_MASK, (dsb_id))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

561

#define LNL_FQ_DSB_SIZE(size) REG_FIELD_PREP(LNL_FQ_DSB_SIZE_MASK, (size))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

576

#define PTL_FQ_DSB_ID(dsb_id) REG_FIELD_PREP(PTL_FQ_DSB_ID_MASK, (dsb_id))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

578

#define PTL_FQ_DSB_SIZE(size) REG_FIELD_PREP(PTL_FQ_DSB_SIZE_MASK, (size))

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

51

#define DP_AUX_CH_CTL_TIME_OUT_400us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 0)

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

52

#define DP_AUX_CH_CTL_TIME_OUT_600us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 1)

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

53

#define DP_AUX_CH_CTL_TIME_OUT_800us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 2)

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

54

#define DP_AUX_CH_CTL_TIME_OUT_MAX REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 3) /* Varies per platform */

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

57

#define DP_AUX_CH_CTL_MESSAGE_SIZE(x) REG_FIELD_PREP(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

59

#define DP_AUX_CH_CTL_PRECHARGE_2US(x) REG_FIELD_PREP(DP_AUX_CH_CTL_PRECHARGE_2US_MASK, (x))

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

72

#define DP_AUX_CH_CTL_BIT_CLOCK_2X(x) REG_FIELD_PREP(DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK, (x))

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

74

#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK, (c) - 1)

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

76

#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

28

#define DSB_MMIO_DEAD_CLOCKS_COUNT(x) REG_FIELD_PREP(DSB_MMIO_DEAD_CLOCK_COUNT_MASK, (x))

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

30

#define DSB_MMIO_CYCLES(x) REG_FIELD_PREP(DSB_MMIO_CYCLES_MASK, (x))

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

34

#define DSB_POLL_WAIT(x) REG_FIELD_PREP(DSB_POLL_WAIT_MASK, (x)) /* usec */

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

36

#define DSB_POLL_COUNT(x) REG_FIELD_PREP(DSB_POLL_COUNT_MASK, (x))

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

71

#define DSB_RM_CLAIM_TIMEOUT_COUNT(x) REG_FIELD_PREP(DSB_RM_CLAIM_TIMEOUT_COUNT_MASK, (x)) /* clocks */

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

73

#define DSB_RM_READY_TIMEOUT_VALUE(x) REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

78

#define DSB_SCANLINE_FOR_DEWAKE(x) REG_FIELD_PREP(DSB_SCANLINE_FOR_DEWAKE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

17

#define DVO_PIPE_SEL(pipe) REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

19

#define DVO_PIPE_STALL_UNUSED REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

20

#define DVO_PIPE_STALL REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

21

#define DVO_PIPE_STALL_TV REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

27

#define DVO_DATA_ORDER_I740 REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

28

#define DVO_DATA_ORDER_FP REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

35

#define DVO_ACT_DATA_ORDER_RGGB REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

36

#define DVO_ACT_DATA_ORDER_GBRG REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

37

#define DVO_ACT_DATA_ORDER_GBRG_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

38

#define DVO_ACT_DATA_ORDER_RGGB_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

50

#define DVO_SRCDIM_HORIZONTAL(x) REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

52

#define DVO_SRCDIM_VERTICAL(x) REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

101

#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

105

#define FBC_DIRTY_RECT_END_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

107

#define FBC_DIRTY_RECT_START_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

119

#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

15

#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

20

#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

22

#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

33

#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

34

#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

35

#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

36

#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

39

#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

46

#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

47

#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

48

#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

49

#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

59

#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

62

#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

66

#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

71

#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

72

#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

73

#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)

sys/dev/pci/drm/i915/display/intel_fbc_regs.h

75

#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))

sys/dev/pci/drm/i915/display/intel_lvds.c

224

REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |

sys/dev/pci/drm/i915/display/intel_lvds.c

225

REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) |

sys/dev/pci/drm/i915/display/intel_lvds.c

226

REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on));

sys/dev/pci/drm/i915/display/intel_lvds.c

229

REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) |

sys/dev/pci/drm/i915/display/intel_lvds.c

230

REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off));

sys/dev/pci/drm/i915/display/intel_lvds.c

233

REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |

sys/dev/pci/drm/i915/display/intel_lvds.c

234

REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

20

#define LVDS_PIPE_SEL(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

22

#define LVDS_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe))

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

36

#define LVDS_A0A2_CLKA_POWER_DOWN REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

37

#define LVDS_A0A2_CLKA_POWER_UP REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

44

#define LVDS_A3_POWER_DOWN REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

45

#define LVDS_A3_POWER_UP REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

51

#define LVDS_CLKB_POWER_DOWN REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

52

#define LVDS_CLKB_POWER_UP REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

59

#define LVDS_B0B3_POWER_DOWN REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

60

#define LVDS_B0B3_POWER_UP REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

13

#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

15

#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

16

#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

17

#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

18

#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

20

#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

21

#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

22

#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

24

#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

27

#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

33

#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

35

#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

48

#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

50

#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

51

#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

52

#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

53

#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

59

#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

61

#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

67

#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

69

#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

16

#define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

17

#define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

18

#define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

19

#define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

20

#define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

21

#define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

22

#define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

23

#define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

26

#define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

27

#define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

28

#define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

31

#define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

32

#define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

33

#define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

35

#define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

36

#define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

39

#define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

40

#define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

41

#define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

43

#define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

44

#define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

45

#define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

48

#define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

49

#define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

50

#define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

52

#define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

53

#define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

54

#define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

55

#define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

56

#define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

505

REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, dbufs));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

545

*(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \

sys/dev/pci/drm/i915/display/intel_pps.c

1637

pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->power_up) |

sys/dev/pci/drm/i915/display/intel_pps.c

1638

REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->backlight_on);

sys/dev/pci/drm/i915/display/intel_pps.c

1639

pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->backlight_off) |

sys/dev/pci/drm/i915/display/intel_pps.c

1640

REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->power_down);

sys/dev/pci/drm/i915/display/intel_pps.c

1673

REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK,

sys/dev/pci/drm/i915/display/intel_pps.c

1675

REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,

sys/dev/pci/drm/i915/display/intel_pps.c

1679

REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK,

sys/dev/pci/drm/i915/display/intel_pps_regs.h

31

#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

32

#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

33

#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

36

#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

37

#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

38

#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

39

#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

40

#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

41

#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

42

#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

43

#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

44

#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

49

#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

59

#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

60

#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

61

#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

62

#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

63

#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

107

#define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

108

#define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

109

#define EDP_PSR_STATUS_STATE_SRDENT REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 2)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

110

#define EDP_PSR_STATUS_STATE_BUFOFF REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 3)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

111

#define EDP_PSR_STATUS_STATE_BUFON REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 4)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

112

#define EDP_PSR_STATUS_STATE_AUXACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 5)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

113

#define EDP_PSR_STATUS_STATE_SRDOFFACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 6)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

115

#define EDP_PSR_STATUS_LINK_FULL_OFF REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

116

#define EDP_PSR_STATUS_LINK_FULL_ON REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

117

#define EDP_PSR_STATUS_LINK_STANDBY REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 2)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

161

#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

162

#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

167

#define EDP_MAX_SU_DISABLE_TIME(t) REG_FIELD_PREP(EDP_MAX_SU_DISABLE_TIME, (t))

sys/dev/pci/drm/i915/display/intel_psr_regs.h

170

#define EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_IO_BUFFER_WAKE_MASK, \

sys/dev/pci/drm/i915/display/intel_psr_regs.h

174

#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \

sys/dev/pci/drm/i915/display/intel_psr_regs.h

178

#define LNL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \

sys/dev/pci/drm/i915/display/intel_psr_regs.h

182

#define EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \

sys/dev/pci/drm/i915/display/intel_psr_regs.h

186

#define TGL_EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_FAST_WAKE_MASK, \

sys/dev/pci/drm/i915/display/intel_psr_regs.h

189

#define EDP_PSR2_TP2_TIME_500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

190

#define EDP_PSR2_TP2_TIME_100us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

191

#define EDP_PSR2_TP2_TIME_2500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 2)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

192

#define EDP_PSR2_TP2_TIME_50us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 3)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

194

#define EDP_PSR2_FRAME_BEFORE_SU(a) REG_FIELD_PREP(EDP_PSR2_FRAME_BEFORE_SU_MASK, (a))

sys/dev/pci/drm/i915/display/intel_psr_regs.h

196

#define EDP_PSR2_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR2_IDLE_FRAMES_MASK, (x))

sys/dev/pci/drm/i915/display/intel_psr_regs.h

225

#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

240

#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

242

#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

247

#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

249

#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

275

#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

276

#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

277

#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

290

#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

291

#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_128_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

292

#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_256_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 2)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

293

#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_512_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 3)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

296

#define ALPM_CTL_ALPM_ENTRY_CHECK(val) REG_FIELD_PREP(ALPM_CTL_ALPM_ENTRY_CHECK_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

299

#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

301

#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

306

#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

308

#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

310

#define ALPM_CTL2_NUMBER_OF_LTTPR(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

312

#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

315

#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

322

#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

324

#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

326

#define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

33

#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

334

#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

336

#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

338

#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

34

#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

340

#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

35

#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 2)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

36

#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 3)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

38

#define EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP_TIME_MASK, (x))

sys/dev/pci/drm/i915/display/intel_psr_regs.h

40

#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK, (x))

sys/dev/pci/drm/i915/display/intel_psr_regs.h

43

#define EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

44

#define EDP_PSR_TP_TP1_TP3 REG_FIELD_PREP(EDP_PSR_TP_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

47

#define EDP_PSR_TP2_TP3_TIME_500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

48

#define EDP_PSR_TP2_TP3_TIME_100us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

49

#define EDP_PSR_TP2_TP3_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 2)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

50

#define EDP_PSR_TP2_TP3_TIME_0us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 3)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

52

#define EDP_PSR_TP4_TIME_0us REG_FIELD_PREP(EDP_PSR_TP4_TIME_MASK, 3) /* ICL+ */

sys/dev/pci/drm/i915/display/intel_psr_regs.h

54

#define EDP_PSR_TP1_TIME_500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 0)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

55

#define EDP_PSR_TP1_TIME_100us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 1)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

56

#define EDP_PSR_TP1_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 2)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

57

#define EDP_PSR_TP1_TIME_0us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 3)

sys/dev/pci/drm/i915/display/intel_psr_regs.h

59

#define EDP_PSR_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR_IDLE_FRAMES_MASK, (x))

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

15

#define SBI_ADDR_VALUE(addr) REG_FIELD_PREP(SBI_ADDR_MASK, (addr))

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

21

#define SBI_CTL_DEST_ICLK REG_FIELD_PREP(SBI_CTL_DEST_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

22

#define SBI_CTL_DEST_MPHY REG_FIELD_PREP(SBI_CTL_DEST_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

24

#define SBI_CTL_OP_IORD REG_FIELD_PREP(SBI_CTL_OP_MASK, 2)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

25

#define SBI_CTL_OP_IOWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 3)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

26

#define SBI_CTL_OP_CRRD REG_FIELD_PREP(SBI_CTL_OP_MASK, 6)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

27

#define SBI_CTL_OP_CRWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 7)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

30

#define SBI_RESPONSE_FAIL REG_FIELD_PREP(SBI_RESPONSE_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

31

#define SBI_RESPONSE_SUCCESS REG_FIELD_PREP(SBI_RESPONSE_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

33

#define SBI_STATUS_BUSY REG_FIELD_PREP(SBI_STATUS_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sbi_regs.h

34

#define SBI_STATUS_READY REG_FIELD_PREP(SBI_STATUS_MASK, 0)

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

264

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, ref_range);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

266

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, pll_params.ana_cp_int) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

267

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, pll_params.ana_cp_prop) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

268

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, ana_cp_int_gs) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

269

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, ana_cp_prop_gs);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

271

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, pll_params.mpll_div5_en) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

272

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_params.tx_clk_div) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

273

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, pll_params.pmix_en) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

274

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, pll_params.mpll_ana_v2i) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

275

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, pll_params.ana_freq_vco);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

277

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, prescaler_divider) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

278

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, pll_params.multiplier) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

279

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, pll_params.hdmi_div);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

281

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

282

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, pll_params.fracn_en) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

283

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, pll_params.fracn_den);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

285

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, pll_params.fracn_quot) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

286

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, pll_params.fracn_rem);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

288

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, pll_params.ssc_up_spread);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

337

pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

338

REG_FIELD_PREP(C10_PLL0_FRACEN, pll_params.fracn_en) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

339

REG_FIELD_PREP(C10_PLL0_PMIX_EN, pll_params.pmix_en) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

340

REG_FIELD_PREP(C10_PLL0_ANA_FREQ_VCO_MASK, pll_params.ana_freq_vco);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

341

pll_state->pll[2] = REG_FIELD_PREP(C10_PLL2_MULTIPLIERL_MASK, pll_params.multiplier);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

342

pll_state->pll[3] = REG_FIELD_PREP(C10_PLL3_MULTIPLIERH_MASK, pll_params.multiplier >> 8);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

343

pll_state->pll[8] = REG_FIELD_PREP(C10_PLL8_SSC_UP_SPREAD, pll_params.ssc_up_spread);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

344

pll_state->pll[9] = REG_FIELD_PREP(C10_PLL9_FRACN_DENL_MASK, pll_params.fracn_den);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

345

pll_state->pll[10] = REG_FIELD_PREP(C10_PLL10_FRACN_DENH_MASK, pll_params.fracn_den >> 8);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

346

pll_state->pll[11] = REG_FIELD_PREP(C10_PLL11_FRACN_QUOT_L_MASK, pll_params.fracn_quot);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

347

pll_state->pll[12] = REG_FIELD_PREP(C10_PLL12_FRACN_QUOT_H_MASK,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

350

pll_state->pll[13] = REG_FIELD_PREP(C10_PLL13_FRACN_REM_L_MASK, pll_params.fracn_rem);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

351

pll_state->pll[14] = REG_FIELD_PREP(C10_PLL14_FRACN_REM_H_MASK, pll_params.fracn_rem >> 8);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

352

pll_state->pll[15] = REG_FIELD_PREP(C10_PLL15_TXCLKDIV_MASK, pll_params.tx_clk_div) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

353

REG_FIELD_PREP(C10_PLL15_HDMIDIV_MASK, pll_params.hdmi_div);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

354

pll_state->pll[16] = REG_FIELD_PREP(C10_PLL16_ANA_CPINT, pll_params.ana_cp_int) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

355

REG_FIELD_PREP(C10_PLL16_ANA_CPINTGS_L, ana_cp_int_gs);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

356

pll_state->pll[17] = REG_FIELD_PREP(C10_PLL17_ANA_CPINTGS_H_MASK, ana_cp_int_gs >> 1) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

357

REG_FIELD_PREP(C10_PLL17_ANA_CPPROP_L_MASK, pll_params.ana_cp_prop);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

359

REG_FIELD_PREP(C10_PLL18_ANA_CPPROP_H_MASK, pll_params.ana_cp_prop >> 2) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

360

REG_FIELD_PREP(C10_PLL18_ANA_CPPROPGS_L_MASK, ana_cp_prop_gs);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

362

pll_state->pll[19] = REG_FIELD_PREP(C10_PLL19_ANA_CPPROPGS_H_MASK, ana_cp_prop_gs >> 3) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

363

REG_FIELD_PREP(C10_PLL19_ANA_V2I_MASK, pll_params.mpll_ana_v2i);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

100

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1000

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1002

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1003

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1005

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

101

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1011

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1013

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1014

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1015

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1016

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1018

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1019

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

102

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1020

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1021

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1022

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1024

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1025

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1026

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1028

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1029

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

103

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1030

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1032

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1033

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1035

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1041

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1043

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1044

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1045

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1046

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1048

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1049

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

105

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1050

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1051

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1052

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1054

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1055

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1056

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1058

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1059

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

106

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1060

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1062

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1063

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1065

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

107

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1071

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1073

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1074

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1075

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1076

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1078

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1079

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

108

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1080

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1081

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1082

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1084

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1085

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1086

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1088

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1089

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

109

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1090

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1092

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1093

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1095

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1101

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1103

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1104

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1105

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1106

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1108

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1109

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

111

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1110

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1111

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1112

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1114

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1115

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1116

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1118

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1119

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

112

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1120

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1122

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1123

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1125

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1131

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1133

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1134

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1135

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1136

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1138

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1139

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

114

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1140

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1141

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1142

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1144

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1145

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1146

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1148

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1149

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

115

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1150

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1152

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1153

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1155

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

116

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1161

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1163

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1164

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1165

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1166

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1168

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1169

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1170

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1171

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1172

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1174

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1175

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1176

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1178

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1179

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

118

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1180

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1182

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1183

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1185

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

119

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1191

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1193

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1194

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1195

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1196

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1198

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1199

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1200

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1201

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1202

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1204

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1205

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1206

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1208

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1209

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1210

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1212

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1213

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1215

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1221

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1223

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1224

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1225

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1226

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1228

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1229

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1230

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1231

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1232

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1234

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1235

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1236

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1238

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1239

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1240

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1242

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1243

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1245

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

125

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1251

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1253

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1254

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1255

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1256

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1258

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1259

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1260

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1261

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1262

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1264

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1265

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1266

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1268

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1269

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

127

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1270

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1272

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1273

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1275

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

128

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1281

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1283

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1284

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1285

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1286

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1288

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1289

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

129

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1290

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1291

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1292

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1294

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1295

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1296

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1298

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1299

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

130

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1300

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1302

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1303

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1305

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1311

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1313

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1314

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1315

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1316

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1318

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1319

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

132

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1320

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1321

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1322

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1324

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1325

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1326

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1328

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1329

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

133

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1330

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1332

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1333

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1335

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

134

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1341

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1343

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1344

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1345

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1346

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1348

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1349

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

135

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1350

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1351

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1352

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1354

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1355

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1356

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1358

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1359

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1360

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1362

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1363

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1365

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

137

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1371

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1373

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1374

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1375

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1376

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1378

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1379

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

138

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1380

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1381

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1382

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1384

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1385

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1386

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1388

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1389

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1390

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1392

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1393

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1395

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

140

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1401

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1403

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1404

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1405

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1406

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1408

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1409

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

141

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1410

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1411

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1412

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1414

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1415

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1416

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1418

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1419

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1420

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1422

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1423

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1425

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1431

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1433

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1434

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1435

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1436

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1438

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1439

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1440

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1441

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1442

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1444

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1445

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1446

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1448

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1449

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1450

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1452

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 30146) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1453

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36699),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1455

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1461

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1463

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1464

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1465

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1466

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1468

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1469

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

147

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1470

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1471

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1472

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1474

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1475

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1476

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1478

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1479

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1480

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1482

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1483

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1485

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

149

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1491

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1493

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1494

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1495

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1496

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1498

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1499

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

150

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1500

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1501

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1502

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1504

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1505

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1506

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1508

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1509

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

151

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1510

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1512

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1513

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1515

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

152

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1521

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1523

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1524

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1525

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1526

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1528

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1529

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1530

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1531

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1532

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1534

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1535

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1536

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1538

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1539

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

154

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1540

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1542

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1543

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1545

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

155

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1551

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1553

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1554

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1555

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1556

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1558

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1559

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

156

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1560

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1561

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1562

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1564

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1565

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1566

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1568

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1569

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1570

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1572

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 64094) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1573

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13631),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1575

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

158

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1581

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1583

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1584

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1585

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1586

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1588

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1589

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

159

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1590

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1591

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1592

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1594

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1595

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1596

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1598

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1599

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1600

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1602

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1603

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1605

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

161

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1611

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1613

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1614

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1615

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1616

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1618

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1619

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

162

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1620

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1621

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1622

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1624

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1625

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1626

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1628

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1629

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1630

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1632

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1633

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1635

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1641

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1643

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1644

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1645

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1646

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1648

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1649

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1650

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1651

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1652

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1654

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1655

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1656

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1658

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1659

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1660

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1662

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1663

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1665

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1671

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1673

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1674

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1675

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1676

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1678

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1679

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

168

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1680

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1681

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1682

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1684

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1685

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1686

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1688

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1689

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1690

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1692

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1693

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1695

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

170

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1701

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1703

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1704

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1705

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1706

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1708

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1709

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

171

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1710

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1711

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1713

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1714

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1715

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1717

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1718

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1719

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

172

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1721

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1722

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1724

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

173

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

175

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

176

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

178

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

179

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

181

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

182

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

188

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

190

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

191

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

192

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

193

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

195

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

196

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

197

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

198

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

199

REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

200

REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

201

REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

202

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

204

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

205

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

207

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

208

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

214

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

215

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

217

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

223

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

225

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

226

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

227

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

228

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

230

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

231

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

232

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

233

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

234

REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

235

REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

236

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

238

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

239

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

241

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

242

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

248

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

249

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

251

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

271

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

273

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

274

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

275

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

276

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

278

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

279

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

280

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

281

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

283

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

284

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

286

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

287

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

288

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

290

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

291

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

293

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

294

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

296

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

302

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

304

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

305

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

306

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

307

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

309

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

310

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

311

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

312

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

314

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

315

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

317

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

318

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

319

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

321

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

322

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

324

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

325

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

327

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

333

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

335

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

336

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

337

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

338

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

340

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

341

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

342

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

343

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

344

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

346

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

347

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

349

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

350

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

351

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

353

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

354

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

356

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

357

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

359

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

365

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

367

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

368

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

369

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

370

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

372

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

373

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

374

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

375

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

377

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

378

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

380

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

381

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

382

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

384

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

385

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

387

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

388

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

390

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

412

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

414

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

415

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

416

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

417

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

419

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

420

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

421

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

422

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

424

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

425

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

426

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

428

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

429

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

430

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

432

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

433

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

435

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

441

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

443

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

444

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

445

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

446

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

448

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

449

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

450

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

451

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

453

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

454

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

455

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

457

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

458

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

459

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

461

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

462

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

464

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

470

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

472

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

473

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

474

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

475

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

477

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

478

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

479

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

480

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

481

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

483

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

484

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

485

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

487

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

488

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

489

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

491

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

492

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

494

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

500

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

502

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

503

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

504

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

505

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

507

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

508

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

509

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

510

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

511

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

513

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

514

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

515

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

517

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

518

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

519

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

521

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

522

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

524

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

531

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

533

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

534

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

535

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

536

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

538

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

539

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

540

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

541

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

542

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

544

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

545

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

546

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

548

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

549

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

550

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

552

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

553

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

555

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

561

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

563

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

564

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

565

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

566

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

568

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

569

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

570

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

571

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

572

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

574

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

575

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

576

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

578

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

579

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

580

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

582

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

583

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

585

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

591

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

593

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

594

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

595

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

596

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

598

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

599

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

600

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

601

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

602

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

604

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

605

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

606

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

608

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

609

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

61

val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

610

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

612

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

613

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

615

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

621

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

623

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

624

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

625

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

626

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

628

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

629

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

630

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

631

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

632

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

634

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

635

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

636

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

638

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

639

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

640

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

642

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

643

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

645

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

651

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

653

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

654

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

655

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

656

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

658

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

659

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

660

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

661

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

662

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

664

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

665

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

666

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

668

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

669

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

670

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

672

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

673

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

675

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

681

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

683

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

684

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

685

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

686

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

688

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

689

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

690

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

691

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

692

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

694

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

695

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

696

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

698

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

699

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

700

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

702

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

703

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

705

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

711

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

713

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

714

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

715

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

716

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

718

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

719

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

720

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

721

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

722

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

724

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

725

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

726

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

728

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

729

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

730

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

732

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

733

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

735

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

741

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

743

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

744

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

745

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

746

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

748

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

749

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

750

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

751

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

752

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

754

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

755

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

756

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

758

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

759

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

760

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

762

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

763

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

765

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

771

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

773

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

774

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

775

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

776

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

778

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

779

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

780

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

781

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

782

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

784

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

785

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

786

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

788

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

789

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

790

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

792

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

793

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

795

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

801

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

803

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

804

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

805

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

806

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

808

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

809

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

810

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

811

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

812

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

814

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

815

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

816

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

818

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

819

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

820

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

822

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

823

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

825

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

83

val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

831

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

833

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

834

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

835

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

836

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

838

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

839

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

84

val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

840

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

841

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

842

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

844

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

845

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

846

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

848

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

849

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

85

val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

850

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

852

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

853

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

855

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

861

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

863

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

864

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

865

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

866

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

868

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

869

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

870

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

871

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

872

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

874

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

875

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

876

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

878

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

879

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

880

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

882

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

883

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

885

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

891

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

893

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

894

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

895

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

896

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

898

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

899

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

900

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

901

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

902

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

904

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

905

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

906

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

908

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

909

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

910

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

912

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

913

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

915

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

921

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

923

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

924

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

925

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

926

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

928

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

929

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

930

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

931

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

932

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

934

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

935

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

936

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

938

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

939

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

940

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

942

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

943

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

945

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

951

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

953

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

954

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

955

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

956

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

958

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

959

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

960

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

961

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

962

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

964

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

965

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

966

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

968

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

969

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

970

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

972

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

973

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

975

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

98

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

981

REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

983

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

984

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

985

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

986

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

988

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

989

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

990

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

991

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

992

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

994

REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

995

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

996

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),

sys/dev/pci/drm/i915/display/intel_snps_phy.c

998

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |

sys/dev/pci/drm/i915/display/intel_snps_phy.c

999

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

103

#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

105

#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

123

#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

124

#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

125

#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

126

#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

127

#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

128

#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

135

#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

136

#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

137

#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

138

#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

157

#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

159

#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

165

#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

167

#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

17

#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

18

#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

19

#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

190

#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

192

#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

20

#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

207

#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

208

#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

209

#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

213

#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

215

#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

241

#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

242

#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

243

#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

244

#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

245

#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

246

#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

247

#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

248

#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

249

#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

250

#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

251

#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

256

#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

257

#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

258

#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

259

#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

26

#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

27

#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

276

#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

278

#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

28

#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

284

#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

286

#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

29

#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

309

#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

311

#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

318

#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

328

#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

330

#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

336

#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

338

#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

358

#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

360

#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

368

#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

370

#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

376

#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

378

#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

384

#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

386

#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

47

#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

49

#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

55

#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

57

#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

80

#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

82

#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

97

#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

98

#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

99

#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

100

#define DSC_PPS0_VER_MAJOR(major) REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

104

#define DSC_PPS1_BPP(bpp) REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

109

#define DSC_PPS2_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

110

#define DSC_PPS2_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

115

#define DSC_PPS3_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

116

#define DSC_PPS3_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

121

#define DSC_PPS4_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

123

#define DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

129

#define DSC_PPS5_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

130

#define DSC_PPS5_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

137

#define DSC_PPS6_FLATNESS_MAX_QP(max_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

138

#define DSC_PPS6_FLATNESS_MIN_QP(min_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

139

#define DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

141

#define DSC_PPS6_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

147

#define DSC_PPS7_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

148

#define DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

153

#define DSC_PPS8_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

155

#define DSC_PPS8_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

161

#define DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

163

#define DSC_PPS9_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

171

#define DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

173

#define DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

175

#define DSC_PPS10_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

176

#define DSC_PPS10_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

182

#define DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame) REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

184

#define DSC_PPS16_SLICE_PER_LINE(slice_per_line) REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

186

#define DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

191

#define DSC_PPS17_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

196

#define DSC_PPS18_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

197

#define DSC_PPS18_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

207

#define DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(rows) REG_FIELD_PREP(DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK, (rows))

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

209

#define DSC_SUPS0_SU_PIC_HEIGHT(h) REG_FIELD_PREP(DSC_SUPS0_SU_PIC_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

40

#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

41

#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

94

#define DSC_PPS0_LINE_BUF_DEPTH(depth) REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

96

#define DSC_PPS0_BPC(bpc) REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

98

#define DSC_PPS0_VER_MINOR(minor) REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor)

sys/dev/pci/drm/i915/display/intel_vga_regs.h

17

#define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_vga_regs.h

19

#define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe))

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

104

#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

106

#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

112

#define EMP_AS_SDP_DB_TL(db_transmit_line) REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

21

#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

24

#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

61

#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

62

#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

63

#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

64

#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

65

#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

66

#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)

sys/dev/pci/drm/i915/display/intel_vrr_regs.h

67

#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

822

val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

823

val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

100

#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

110

#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

120

#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

122

#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

132

#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

134

#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

172

#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

182

#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

184

#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

211

#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

230

#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

231

#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

232

#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

233

#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

236

#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

237

#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

238

#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

241

#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

242

#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

243

#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

258

#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

259

#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

260

#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

261

#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

262

#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

265

#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

266

#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

267

#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

380

#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

382

#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

393

#define PLANE_MIN_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

395

#define PLANE_INTERIM_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

40

#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

50

#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

51

#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

52

#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

53

#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

54

#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

55

#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

56

#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

57

#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

58

#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

59

#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

60

#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

61

#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

62

#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

63

#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

64

#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

65

#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

66

#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

69

#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

70

#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

75

#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

76

#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

77

#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

78

#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

84

#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

85

#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

86

#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

87

#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

88

#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

93

#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

94

#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

95

#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

97

#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

98

#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

99

#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)

sys/dev/pci/drm/i915/display/skl_watermark.c

2934

REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time) |

sys/dev/pci/drm/i915/display/skl_watermark.c

2935

REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency));

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

16

#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

18

#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

21

#define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

22

#define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

23

#define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

25

#define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

27

#define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

29

#define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

38

#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

39

#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

41

#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

44

#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

66

#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

68

#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

102

#define DPIO_PCS_TX2MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

103

#define DPIO_PCS_TX2MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

105

#define DPIO_PCS_TX1MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

106

#define DPIO_PCS_TX1MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

114

#define DPIO_PCS_TX2DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

115

#define DPIO_PCS_TX2DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

117

#define DPIO_PCS_TX1DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

118

#define DPIO_PCS_TX1DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

124

#define DPIO_TX2_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

133

#define DPIO_TX2_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

135

#define DPIO_TX1_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

137

#define DPIO_TX1_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

140

#define DPIO_LANESTAGGER_STRAP(x) REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

158

#define DPIO_SWING_MARGIN000(x) REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

160

#define DPIO_UNIQ_TRANS_SCALE(x) REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

167

#define DPIO_SWING_MARGIN101(x) REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

172

#define DPIO_SWING_DEEMPH9P5(x) REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

174

#define DPIO_SWING_DEEMPH6P0_SHIFT REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

189

#define DPIO_CHV_M2_DIV(m2) REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

193

#define DPIO_CHV_N_DIV(n) REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

195

#define DPIO_CHV_M1_DIV(m1) REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

200

#define DPIO_CHV_M2_FRAC_DIV(m2_frac) REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

206

#define DPIO_CHV_FEEDFWD_GAIN(x) REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

210

#define DPIO_CHV_GAIN_CTRL(x) REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

212

#define DPIO_CHV_INT_COEFF(x) REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

214

#define DPIO_CHV_PROP_COEFF(x) REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

218

#define DPIO_CHV_TDC_TARGET_CNT(x) REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

222

#define DPIO_CHV_INT_LOCK_THRESHOLD(x) REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

233

#define CHV_BUFRIGHTENA1_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

234

#define CHV_BUFRIGHTENA1_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

235

#define CHV_BUFRIGHTENA1_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

237

#define CHV_BUFLEFTENA1_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

238

#define CHV_BUFLEFTENA1_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

239

#define CHV_BUFLEFTENA1_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

244

#define DPIO_CHV_S1_DIV(s1) REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

246

#define DPIO_CHV_P1_DIV(p1) REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

248

#define DPIO_CHV_P2_DIV(p2) REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

250

#define DPIO_CHV_K_DIV(k) REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

260

#define CHV_BUFLEFTENA2_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

261

#define CHV_BUFLEFTENA2_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

262

#define CHV_BUFLEFTENA2_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

264

#define CHV_BUFRIGHTENA2_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

265

#define CHV_BUFRIGHTENA2_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

266

#define CHV_BUFRIGHTENA2_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

28

#define DPIO_S1_DIV(s1) REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

281

#define DPIO_SUS_CLK_CONFIG_ON REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

282

#define DPIO_SUS_CLK_CONFIG_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

283

#define DPIO_SUS_CLK_CONFIG_GATE REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

284

#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

304

#define DPIO_FRC_LATENCY(x) REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

34

#define DPIO_K_DIV(k) REG_FIELD_PREP(DPIO_K_DIV_MASK, (k))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

36

#define DPIO_P1_DIV(p1) REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

38

#define DPIO_P2_DIV(p2) REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

40

#define DPIO_N_DIV(n) REG_FIELD_PREP(DPIO_N_DIV_MASK, (n))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

43

#define DPIO_M1_DIV(m1) REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

45

#define DPIO_M2_DIV(m2) REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2))

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

87

#define DPIO_PCS_CLK_DATAWIDTH_8_10 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

88

#define DPIO_PCS_CLK_DATAWIDTH_16_20 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)

sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h

89

#define DPIO_PCS_CLK_DATAWIDTH_32_40 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

129

REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1)

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

142

(REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

143

REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

159

(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \

sys/dev/pci/drm/i915/gt/intel_engine_regs.h

160

REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

250

REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

252

REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

264

REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

266

REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

330

~REG_FIELD_PREP(ENGINE1_MASK, heci_mask));

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

335

REG_FIELD_PREP(ENGINE0_MASK, guc_mask) :

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

336

REG_FIELD_PREP(ENGINE1_MASK, guc_mask);

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

339

REG_FIELD_PREP(ENGINE1_MASK, guc_mask));

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

225

REG_FIELD_PREP(MTL_MCR_GROUPID, group) |

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

226

REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance) |

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1137

#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

1166

#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

34

#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

35

#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

36

#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

37

#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

39

#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

40

#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

436

#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

438

#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

884

#define CTC_SOURCE_CRYSTAL_CLOCK REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 0)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

885

#define CTC_SOURCE_DIVIDE_LOGIC REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 1)

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

945

#define GEN11_HASH_CTRL_EXCL_BIT0 REG_FIELD_PREP(GEN11_HASH_CTRL_EXCL_MASK, 0x1)

sys/dev/pci/drm/i915/gt/intel_gtt.h

160

#define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3)

sys/dev/pci/drm/i915/gt/intel_gtt.h

161

#define MTL_PPAT_L4_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1)

sys/dev/pci/drm/i915/gt/intel_gtt.h

162

#define MTL_PPAT_L4_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0)

sys/dev/pci/drm/i915/gt/intel_gtt.h

163

#define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3)

sys/dev/pci/drm/i915/gt/intel_gtt.h

164

#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1339

*cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2866

REG_FIELD_PREP(MAXREQS_PER_BANK, 2));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

708

REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4975

REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_TYPE_MASK, type) |

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4976

REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_MODE_MASK,

sys/dev/pci/drm/i915/i915_hwmon.c

245

rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);

sys/dev/pci/drm/i915/i915_hwmon.c

487

nval = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, nval);

sys/dev/pci/drm/i915/i915_reg.h

1031

#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */

sys/dev/pci/drm/i915/i915_reg.h

1124

#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))

sys/dev/pci/drm/i915/i915_reg.h

1125

#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))

sys/dev/pci/drm/i915/i915_reg.h

1126

#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))

sys/dev/pci/drm/i915/i915_reg.h

1133

#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)

sys/dev/pci/drm/i915/i915_reg.h

1134

#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)

sys/dev/pci/drm/i915/i915_reg.h

1135

#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)

sys/dev/pci/drm/i915/i915_reg.h

1137

#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)

sys/dev/pci/drm/i915/i915_reg.h

1138

#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)

sys/dev/pci/drm/i915/i915_reg.h

1139

#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)

sys/dev/pci/drm/i915/i915_reg.h

1141

#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))

sys/dev/pci/drm/i915/i915_reg.h

1143

#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))

sys/dev/pci/drm/i915/i915_reg.h

588

#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)

sys/dev/pci/drm/i915/i915_reg.h

589

#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)

sys/dev/pci/drm/i915/i915_reg.h

590

#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)

sys/dev/pci/drm/i915/i915_reg.h

591

#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)

sys/dev/pci/drm/i915/i915_reg.h

593

#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)

sys/dev/pci/drm/i915/i915_reg.h

594

#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)

sys/dev/pci/drm/i915/i915_reg.h

595

#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)

sys/dev/pci/drm/i915/i915_reg.h

596

#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)

sys/dev/pci/drm/i915/i915_reg.h

961

#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)

sys/dev/pci/drm/i915/i915_reg.h

962

#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)

sys/dev/pci/drm/i915/i915_reg.h

963

#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)

sys/dev/pci/drm/i915/i915_reg.h

964

#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)

sys/dev/pci/drm/i915/i915_reg.h

966

#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)

sys/dev/pci/drm/i915/i915_reg.h

967

#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)

sys/dev/pci/drm/i915/i915_reg.h

968

#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)

sys/dev/pci/drm/i915/i915_reg.h

969

#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)

sys/dev/pci/drm/i915/i915_reg.h

974

#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)

sys/dev/pci/drm/i915/i915_reg.h

975

#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)

sys/dev/pci/drm/i915/i915_reg.h

976

#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)

sys/dev/pci/drm/i915/i915_reg.h

977

#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)

sys/dev/pci/drm/i915/intel_pcode.c

251

mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)

sys/dev/pci/drm/i915/intel_pcode.c

252

| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)

sys/dev/pci/drm/i915/intel_pcode.c

253

| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);

sys/dev/pci/drm/i915/intel_pcode.c

267

mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)

sys/dev/pci/drm/i915/intel_pcode.c

268

| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)

sys/dev/pci/drm/i915/intel_pcode.c

269

| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);