sys/dev/pci/drm/i915/display/g4x_dp.c

289

*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val);

sys/dev/pci/drm/i915/display/g4x_dp.c

293

*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val);

sys/dev/pci/drm/i915/display/g4x_dp.c

295

*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/g4x_dp.c

390

pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1232

fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1233

fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;

sys/dev/pci/drm/i915/display/i9xx_plane.c

748

*pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2771

wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2772

wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2773

wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2774

wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2788

wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2789

wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3520

active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3521

active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3522

active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_audio.c

262

return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_bw.c

105

sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);

sys/dev/pci/drm/i915/display/intel_bw.c

106

sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);

sys/dev/pci/drm/i915/display/intel_bw.c

109

sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);

sys/dev/pci/drm/i915/display/intel_bw.c

110

sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);

sys/dev/pci/drm/i915/display/intel_bw.c

230

dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);

sys/dev/pci/drm/i915/display/intel_bw.c

232

sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);

sys/dev/pci/drm/i915/display/intel_bw.c

233

sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);

sys/dev/pci/drm/i915/display/intel_bw.c

235

sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);

sys/dev/pci/drm/i915/display/intel_bw.c

236

sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);

sys/dev/pci/drm/i915/display/intel_bw.c

90

dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1783

size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1784

waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);

sys/dev/pci/drm/i915/display/intel_color.c

1839

entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, ldw), 14);

sys/dev/pci/drm/i915/display/intel_color.c

1840

entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, ldw), 14);

sys/dev/pci/drm/i915/display/intel_color.c

1841

entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_RED_UDW_MASK, udw), 14);

sys/dev/pci/drm/i915/display/intel_color.c

1873

entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_LDW_MASK, ldw), 10);

sys/dev/pci/drm/i915/display/intel_color.c

1874

entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_LDW_MASK, ldw), 10);

sys/dev/pci/drm/i915/display/intel_color.c

1875

entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_UDW_MASK, udw), 10);

sys/dev/pci/drm/i915/display/intel_color.c

828

entry->red = intel_color_lut_pack(REG_FIELD_GET(PALETTE_RED_MASK, val), 8);

sys/dev/pci/drm/i915/display/intel_color.c

829

entry->green = intel_color_lut_pack(REG_FIELD_GET(PALETTE_GREEN_MASK, val), 8);

sys/dev/pci/drm/i915/display/intel_color.c

830

entry->blue = intel_color_lut_pack(REG_FIELD_GET(PALETTE_BLUE_MASK, val), 8);

sys/dev/pci/drm/i915/display/intel_color.c

877

u16 red = REG_FIELD_GET(PALETTE_10BIT_RED_LDW_MASK, ldw) |

sys/dev/pci/drm/i915/display/intel_color.c

878

REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8;

sys/dev/pci/drm/i915/display/intel_color.c

879

u16 green = REG_FIELD_GET(PALETTE_10BIT_GREEN_LDW_MASK, ldw) |

sys/dev/pci/drm/i915/display/intel_color.c

880

REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8;

sys/dev/pci/drm/i915/display/intel_color.c

881

u16 blue = REG_FIELD_GET(PALETTE_10BIT_BLUE_LDW_MASK, ldw) |

sys/dev/pci/drm/i915/display/intel_color.c

882

REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8;

sys/dev/pci/drm/i915/display/intel_color.c

892

int r_exp = REG_FIELD_GET(PALETTE_10BIT_RED_EXP_MASK, udw);

sys/dev/pci/drm/i915/display/intel_color.c

893

int r_mant = REG_FIELD_GET(PALETTE_10BIT_RED_MANT_MASK, udw);

sys/dev/pci/drm/i915/display/intel_color.c

894

int g_exp = REG_FIELD_GET(PALETTE_10BIT_GREEN_EXP_MASK, udw);

sys/dev/pci/drm/i915/display/intel_color.c

895

int g_mant = REG_FIELD_GET(PALETTE_10BIT_GREEN_MANT_MASK, udw);

sys/dev/pci/drm/i915/display/intel_color.c

896

int b_exp = REG_FIELD_GET(PALETTE_10BIT_BLUE_EXP_MASK, udw);

sys/dev/pci/drm/i915/display/intel_color.c

897

int b_mant = REG_FIELD_GET(PALETTE_10BIT_BLUE_MANT_MASK, udw);

sys/dev/pci/drm/i915/display/intel_color.c

924

entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |

sys/dev/pci/drm/i915/display/intel_color.c

925

REG_FIELD_GET(PALETTE_RED_MASK, ldw);

sys/dev/pci/drm/i915/display/intel_color.c

926

entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |

sys/dev/pci/drm/i915/display/intel_color.c

927

REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);

sys/dev/pci/drm/i915/display/intel_color.c

928

entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |

sys/dev/pci/drm/i915/display/intel_color.c

929

REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);

sys/dev/pci/drm/i915/display/intel_color.c

947

entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_RED_MASK, val), 10);

sys/dev/pci/drm/i915/display/intel_color.c

948

entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_GREEN_MASK, val), 10);

sys/dev/pci/drm/i915/display/intel_color.c

949

entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_BLUE_MASK, val), 10);

sys/dev/pci/drm/i915/display/intel_color.c

970

entry->red = REG_FIELD_GET(PREC_PALETTE_12P4_RED_UDW_MASK, udw) << 6 |

sys/dev/pci/drm/i915/display/intel_color.c

971

REG_FIELD_GET(PREC_PALETTE_12P4_RED_LDW_MASK, ldw);

sys/dev/pci/drm/i915/display/intel_color.c

972

entry->green = REG_FIELD_GET(PREC_PALETTE_12P4_GREEN_UDW_MASK, udw) << 6 |

sys/dev/pci/drm/i915/display/intel_color.c

973

REG_FIELD_GET(PREC_PALETTE_12P4_GREEN_LDW_MASK, ldw);

sys/dev/pci/drm/i915/display/intel_color.c

974

entry->blue = REG_FIELD_GET(PREC_PALETTE_12P4_BLUE_UDW_MASK, udw) << 6 |

sys/dev/pci/drm/i915/display/intel_color.c

975

REG_FIELD_GET(PREC_PALETTE_12P4_BLUE_LDW_MASK, ldw);

sys/dev/pci/drm/i915/display/intel_crt.c

100

*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val);

sys/dev/pci/drm/i915/display/intel_crt.c

102

*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/intel_crt.c

717

vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;

sys/dev/pci/drm/i915/display/intel_crt.c

718

vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;

sys/dev/pci/drm/i915/display/intel_crt.c

720

vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;

sys/dev/pci/drm/i915/display/intel_crt.c

721

vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;

sys/dev/pci/drm/i915/display/intel_crt.c

757

u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;

sys/dev/pci/drm/i915/display/intel_cursor.c

751

*pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

198

if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2398

unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2402

frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2406

multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2407

tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2408

ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2412

frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2416

multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2417

tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2418

ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2419

fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

247

return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

203

REG_FIELD_GET(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \

sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h

204

REG_FIELD_GET(_XELPDP_DDI_CLOCK_SELECT_MASK, (val)))

sys/dev/pci/drm/i915/display/intel_ddi.c

2523

pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);

sys/dev/pci/drm/i915/display/intel_ddi.c

3935

master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);

sys/dev/pci/drm/i915/display/intel_ddi.c

3943

master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);

sys/dev/pci/drm/i915/display/intel_ddi.c

4050

REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);

sys/dev/pci/drm/i915/display/intel_ddi.c

4086

REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);

sys/dev/pci/drm/i915/display/intel_display.c

2847

adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2848

adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2853

adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2854

adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2858

adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2859

adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2862

adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2863

adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2869

adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2870

adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2873

adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2874

adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

2919

REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,

sys/dev/pci/drm/i915/display/intel_display.c

2920

REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);

sys/dev/pci/drm/i915/display/intel_display.c

3064

pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);

sys/dev/pci/drm/i915/display/intel_display.c

3066

pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

3322

m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

3413

pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);

sys/dev/pci/drm/i915/display/intel_display.c

3415

pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

3417

pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_display.c

3980

pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_display.c

3983

REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_display.c

4007

pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;

sys/dev/pci/drm/i915/display/intel_display_device.c

1557

gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);

sys/dev/pci/drm/i915/display/intel_display_device.c

1558

gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);

sys/dev/pci/drm/i915/display/intel_display_device.c

1559

gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);

sys/dev/pci/drm/i915/display/intel_display_device.c

1914

if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) ==

sys/dev/pci/drm/i915/display/intel_display_device.c

1918

if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) ==

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1606

actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 |

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1609

actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 |

sys/dev/pci/drm/i915/display/intel_dmc.c

550

REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

416

recv_bytes = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, status);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

814

stream_type = REG_FIELD_GET(AUTH_STREAM_TYPE_MASK, val);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

836

stream_type = REG_FIELD_GET(STREAM_TYPE_STATUS_MASK, val);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

387

return REG_FIELD_GET(GRC_CODE_MASK, val);

sys/dev/pci/drm/i915/display/intel_dpll.c

534

clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

535

clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

536

clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

537

clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

538

clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

566

clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;

sys/dev/pci/drm/i915/display/intel_dpll.c

567

clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22;

sys/dev/pci/drm/i915/display/intel_dpll.c

569

clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2);

sys/dev/pci/drm/i915/display/intel_dpll.c

570

clock.n = REG_FIELD_GET(DPIO_CHV_N_DIV_MASK, pll_dw1);

sys/dev/pci/drm/i915/display/intel_dpll.c

571

clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13);

sys/dev/pci/drm/i915/display/intel_dpll.c

572

clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2378

clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2380

clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2382

clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, hw_state->pll1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2383

clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2384

clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);

sys/dev/pci/drm/i915/display/intel_dvo.c

156

*pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_flipq.c

247

REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, tmp),

sys/dev/pci/drm/i915/display/intel_flipq.c

248

REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, tmp),

sys/dev/pci/drm/i915/display/intel_flipq.c

249

REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, tmp),

sys/dev/pci/drm/i915/display/intel_flipq.c

250

REG_FIELD_GET(PIPEDMC_FPQ_GENERALQ_TP_MASK, tmp),

sys/dev/pci/drm/i915/display/intel_flipq.c

251

REG_FIELD_GET(PIPEDMC_FPQ_FASTQ_TP_MASK, tmp));

sys/dev/pci/drm/i915/display/intel_hti.c

42

return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state);

sys/dev/pci/drm/i915/display/intel_lvds.c

166

pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

167

pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

168

pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

171

pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

172

pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

175

pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

176

val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

96

*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

98

*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/intel_overlay.c

958

ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);

sys/dev/pci/drm/i915/display/intel_overlay.c

967

ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_pfit.c

631

pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);

sys/dev/pci/drm/i915/display/intel_pfit.c

641

REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),

sys/dev/pci/drm/i915/display/intel_pfit.c

642

REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),

sys/dev/pci/drm/i915/display/intel_pfit.c

643

REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),

sys/dev/pci/drm/i915/display/intel_pfit.c

644

REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));

sys/dev/pci/drm/i915/display/intel_pfit.c

721

pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

422

REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

424

REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

426

REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

428

REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

431

REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

433

REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

437

REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

440

REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

442

REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

445

REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

540

u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \

sys/dev/pci/drm/i915/display/intel_pps.c

1407

seq->power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);

sys/dev/pci/drm/i915/display/intel_pps.c

1408

seq->backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);

sys/dev/pci/drm/i915/display/intel_pps.c

1409

seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);

sys/dev/pci/drm/i915/display/intel_pps.c

1410

seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);

sys/dev/pci/drm/i915/display/intel_pps.c

1417

power_cycle_delay = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div);

sys/dev/pci/drm/i915/display/intel_pps.c

1419

power_cycle_delay = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl);

sys/dev/pci/drm/i915/display/intel_psr.c

1788

pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val);

sys/dev/pci/drm/i915/display/intel_psr.c

3997

status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);

sys/dev/pci/drm/i915/display/intel_psr.c

4013

status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val);

sys/dev/pci/drm/i915/display/intel_psr.c

4129

REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1930

refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1932

frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1935

frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1936

frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1937

frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1940

multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1942

tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);

sys/dev/pci/drm/i915/display/intel_vdsc.c

910

vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

911

vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

922

vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

932

vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances;

sys/dev/pci/drm/i915/display/intel_vdsc.c

933

vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

938

vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

939

vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

944

vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

945

vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

950

vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

951

vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

956

vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

957

vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

958

vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

959

vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

964

vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

965

vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

970

vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

971

vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

976

vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

981

vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

982

vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

987

vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

993

vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

998

vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vdsc.c

999

vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);

sys/dev/pci/drm/i915/display/intel_vga.c

58

pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp);

sys/dev/pci/drm/i915/display/intel_vga.c

60

pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_vrr.c

742

REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);

sys/dev/pci/drm/i915/display/intel_vrr.c

746

REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);

sys/dev/pci/drm/i915/display/intel_vrr.c

771

REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync);

sys/dev/pci/drm/i915/display/intel_vrr.c

773

REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync);

sys/dev/pci/drm/i915/display/skl_scaler.c

930

REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),

sys/dev/pci/drm/i915/display/skl_scaler.c

931

REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),

sys/dev/pci/drm/i915/display/skl_scaler.c

932

REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),

sys/dev/pci/drm/i915/display/skl_scaler.c

933

REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3053

alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3055

alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3152

fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3153

fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3158

fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;

sys/dev/pci/drm/i915/display/skl_watermark.c

110

return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

2921

latency = REG_FIELD_GET(LNL_PKG_C_LATENCY_MASK,

sys/dev/pci/drm/i915/display/skl_watermark.c

3002

level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

3003

level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

3227

wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

3228

wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

3231

wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

3232

wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

3235

wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

3236

wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

3257

wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;

sys/dev/pci/drm/i915/display/skl_watermark.c

3258

wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;

sys/dev/pci/drm/i915/display/skl_watermark.c

3259

wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;

sys/dev/pci/drm/i915/display/skl_watermark.c

3260

wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;

sys/dev/pci/drm/i915/display/skl_watermark.c

3270

wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;

sys/dev/pci/drm/i915/display/skl_watermark.c

3271

wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;

sys/dev/pci/drm/i915/display/skl_watermark.c

3272

wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;

sys/dev/pci/drm/i915/display/skl_watermark.c

3273

wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;

sys/dev/pci/drm/i915/display/skl_watermark.c

663

REG_FIELD_GET(PLANE_BUF_START_MASK, reg),

sys/dev/pci/drm/i915/display/skl_watermark.c

664

REG_FIELD_GET(PLANE_BUF_END_MASK, reg));

sys/dev/pci/drm/i915/display/skl_watermark.c

692

*min_ddb = REG_FIELD_GET(PLANE_MIN_DBUF_BLOCKS_MASK, val);

sys/dev/pci/drm/i915/display/skl_watermark.c

693

*interim_ddb = REG_FIELD_GET(PLANE_INTERIM_DBUF_BLOCKS_MASK, val);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

911

gms = REG_FIELD_GET(GMS_MASK, ggc);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

776

vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

777

vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

781

gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);

sys/dev/pci/drm/i915/gt/intel_gt.c

320

REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),

sys/dev/pci/drm/i915/gt/intel_gt.c

321

REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));

sys/dev/pci/drm/i915/gt/intel_gt.c

342

REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),

sys/dev/pci/drm/i915/gt/intel_gt.c

343

REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),

sys/dev/pci/drm/i915/gt/intel_gt.c

344

REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

102

freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg);

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

81

freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

125

gt->info.mslice_mask |= REG_FIELD_GET(GEN12_MEML3_EN_MASK,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

138

fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

142

fuse = REG_FIELD_GET(GT_L3_EXC_MASK,

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

291

switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

359

REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat));

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

627

mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?

sys/dev/pci/drm/i915/gt/intel_rps.c

1131

caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap);

sys/dev/pci/drm/i915/gt/intel_rps.c

1132

caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap);

sys/dev/pci/drm/i915/gt/intel_rps.c

1133

caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe);

sys/dev/pci/drm/i915/gt/intel_rps.c

1152

caps->rp1_freq = REG_FIELD_GET(RPE_MASK,

sys/dev/pci/drm/i915/gt/intel_rps.c

2102

cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);

sys/dev/pci/drm/i915/gt/intel_rps.c

2104

cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);

sys/dev/pci/drm/i915/gt/intel_rps.c

2106

cagf = REG_FIELD_GET(RPE_MASK, rpstat);

sys/dev/pci/drm/i915/gt/intel_rps.c

2108

cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);

sys/dev/pci/drm/i915/gt/intel_rps.c

2110

cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat);

sys/dev/pci/drm/i915/gt/intel_rps.c

2112

cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat);

sys/dev/pci/drm/i915/gt/intel_rps.c

2114

cagf = gen5_invert_freq(rps, REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rpstat));

sys/dev/pci/drm/i915/gt/intel_sseu.c

239

eu_en_fuse = REG_FIELD_GET(XEHP_EU_ENA_MASK,

sys/dev/pci/drm/i915/gt/intel_sseu.c

273

s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,

sys/dev/pci/drm/i915/gt/intel_sseu.c

280

eu_en_fuse = ~REG_FIELD_GET(GEN11_EU_DIS_MASK,

sys/dev/pci/drm/i915/gt/intel_sseu.c

310

s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,

sys/dev/pci/drm/i915/gt/intel_sseu.c

316

eu_en = ~REG_FIELD_GET(GEN11_EU_DIS_MASK,

sys/dev/pci/drm/i915/gt/intel_sseu.c

339

REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R0_MASK, fuse) |

sys/dev/pci/drm/i915/gt/intel_sseu.c

340

REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK);

sys/dev/pci/drm/i915/gt/intel_sseu.c

348

REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R0_MASK, fuse) |

sys/dev/pci/drm/i915/gt/intel_sseu.c

349

REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK);

sys/dev/pci/drm/i915/gt/intel_sseu.c

385

sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);

sys/dev/pci/drm/i915/gt/intel_sseu.c

396

subslice_mask &= ~REG_FIELD_GET(GEN9_F2_SS_DIS_MASK, fuse2);

sys/dev/pci/drm/i915/gt/intel_sseu.c

489

sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);

sys/dev/pci/drm/i915/gt/intel_sseu.c

497

subslice_mask &= ~REG_FIELD_GET(GEN8_F2_SS_DIS_MASK, fuse2);

sys/dev/pci/drm/i915/gt/intel_sseu.c

502

REG_FIELD_GET(GEN8_EU_DIS0_S0_MASK, eu_disable0);

sys/dev/pci/drm/i915/gt/intel_sseu.c

504

REG_FIELD_GET(GEN8_EU_DIS0_S1_MASK, eu_disable0) |

sys/dev/pci/drm/i915/gt/intel_sseu.c

505

REG_FIELD_GET(GEN8_EU_DIS1_S1_MASK, eu_disable1) << hweight32(GEN8_EU_DIS0_S1_MASK);

sys/dev/pci/drm/i915/gt/intel_sseu.c

507

REG_FIELD_GET(GEN8_EU_DIS1_S2_MASK, eu_disable1) |

sys/dev/pci/drm/i915/gt/intel_sseu.c

508

REG_FIELD_GET(GEN8_EU_DIS2_S2_MASK, eu_disable2) << hweight32(GEN8_EU_DIS1_S2_MASK);

sys/dev/pci/drm/i915/gt/intel_sseu.c

596

switch (REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1)) {

sys/dev/pci/drm/i915/gt/intel_sseu.c

598

MISSING_CASE(REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1));

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

21

return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) ==

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

42

return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE,

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

110

u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

111

u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

207

REG_FIELD_GET(GS_BOOTROM_MASK, status),

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

208

REG_FIELD_GET(GS_UKERNEL_MASK, status));

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

214

u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

215

u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

220

REG_FIELD_GET(GS_MIA_IN_RESET, status),

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

222

REG_FIELD_GET(GS_MIA_MASK, status),

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

223

REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

377

return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

388

return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1293

return 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);

sys/dev/pci/drm/i915/gvt/edid.c

497

msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, value);

sys/dev/pci/drm/i915/gvt/handlers.c

1421

sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));

sys/dev/pci/drm/i915/gvt/handlers.c

1448

sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));

sys/dev/pci/drm/i915/gvt/handlers.c

585

clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,

sys/dev/pci/drm/i915/gvt/handlers.c

588

clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,

sys/dev/pci/drm/i915/gvt/handlers.c

590

clock.n = REG_FIELD_GET(PORT_PLL_N_MASK,

sys/dev/pci/drm/i915/gvt/handlers.c

592

clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK,

sys/dev/pci/drm/i915/gvt/handlers.c

594

clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK,

sys/dev/pci/drm/i915/i915_hwmon.c

110

reg_value = REG_FIELD_GET(field_msk, reg_value);

sys/dev/pci/drm/i915/i915_hwmon.c

180

x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);

sys/dev/pci/drm/i915/i915_hwmon.c

181

y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);

sys/dev/pci/drm/i915/i915_hwmon.c

224

x = REG_FIELD_GET(PKG_MAX_WIN_X, r);

sys/dev/pci/drm/i915/i915_hwmon.c

225

y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);

sys/dev/pci/drm/i915/i915_hwmon.c

340

*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;

sys/dev/pci/drm/i915/i915_hwmon.c

372

*val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10);

sys/dev/pci/drm/i915/i915_hwmon.c

430

min = REG_FIELD_GET(PKG_MIN_PWR, r);

sys/dev/pci/drm/i915/i915_hwmon.c

432

max = REG_FIELD_GET(PKG_MAX_PWR, r);

sys/dev/pci/drm/i915/i915_hwmon.c

520

*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),

sys/dev/pci/drm/i915/i915_hwmon.c

637

*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),

sys/dev/pci/drm/i915/i915_hwmon.c

888

hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);

sys/dev/pci/drm/i915/i915_hwmon.c

889

hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);

sys/dev/pci/drm/i915/i915_hwmon.c

890

hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);

sys/dev/pci/drm/i915/i915_perf.c

3234

shift = REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,

sys/dev/pci/drm/i915/intel_clock_gating.c

244

if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12)

sys/dev/pci/drm/i915/intel_device_info.c

319

ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);

sys/dev/pci/drm/i915/intel_device_info.c

320

ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);

sys/dev/pci/drm/i915/intel_device_info.c

321

ip->step = REG_FIELD_GET(GMD_ID_STEP, val);

sys/dev/pci/drm/i915/soc/intel_dram.c

690

switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {

sys/dev/pci/drm/i915/soc/intel_dram.c

722

dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);

sys/dev/pci/drm/i915/soc/intel_dram.c

723

dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);