sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
104
#define PHY_POWER_GOOD REG_BIT(16)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
105
#define PHY_RESERVED REG_BIT(7)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
122
#define OCL1_POWER_DOWN_EN REG_BIT(23)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
123
#define DW28_OLDO_DYN_PWR_DOWN_EN REG_BIT(22)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
129
#define OCL2_LDOFUSE_PWR_DIS REG_BIT(6)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
138
#define DW6_OLDO_DYN_PWR_DOWN_EN REG_BIT(28)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
143
#define GRC_DONE REG_BIT(22)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
160
#define GRC_DIS REG_BIT(15)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
161
#define GRC_RDY_OVRD REG_BIT(1)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
178
#define TX2_SWING_CALC_INIT REG_BIT(31)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
179
#define TX1_SWING_CALC_INIT REG_BIT(30)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
190
#define LANESTAGGER_STRAP_OVRD REG_BIT(6)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
232
#define SCALE_DCOMP_METHOD REG_BIT(26)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
233
#define UNIQUE_TRANGE_EN_METHOD REG_BIT(27)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
262
#define DCC_DELAY_RANGE_1 REG_BIT(9)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
263
#define DCC_DELAY_RANGE_2 REG_BIT(8)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
268
#define LATENCY_OPTIM REG_BIT(30)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
37
#define PORT_PLL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
38
#define PORT_PLL_LOCK REG_BIT(30)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
39
#define PORT_PLL_REF_SEL REG_BIT(27)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
40
#define PORT_PLL_POWER_ENABLE REG_BIT(26)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
41
#define PORT_PLL_POWER_STATE REG_BIT(25)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
58
#define PORT_PLL_RECALIBRATE REG_BIT(14)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
59
#define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
77
#define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
92
#define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
108
#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
16
#define DISP_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
17
#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
32
#define DISP_STEREO_ENABLE REG_BIT(25)
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
33
#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
36
#define DISP_SRC_KEY_ENABLE REG_BIT(22)
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
37
#define DISP_LINE_DOUBLE REG_BIT(20)
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
38
#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
39
#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
40
#define DISP_ROTATE_180 REG_BIT(15) /* i965+ */
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
41
#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) /* pre-g4x plane B */
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
42
#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
43
#define DISP_TILED REG_BIT(10) /* i965+ */
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
44
#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
45
#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
sys/dev/pci/drm/i915/display/i9xx_plane_regs.h
46
#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) /* pre-g4x plane B/C */
sys/dev/pci/drm/i915/display/i9xx_wm_regs.h
231
#define WM_LP_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/i9xx_wm_regs.h
245
#define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
sys/dev/pci/drm/i915/display/intel_audio_regs.h
12
#define G4X_ELD_VALID REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
122
#define AUD_ENABLE_SDP_SPLIT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
125
#define SKL_AUD_CODEC_WAKE_SIGNAL REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
129
#define AUD_PIN_BUF_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
132
#define AUD_TS_CDCLK_M_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
15
#define G4X_ELD_ACK REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
168
#define DACBE_DISABLE_MIN_HBLANK_FIX REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
28
#define IBX_ELD_ACK REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
30
#define IBX_CP_READY(port) REG_BIT(((port) - 1) * 4 + 1)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
31
#define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
58
#define AUD_CONFIG_N_VALUE_INDEX REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
59
#define AUD_CONFIG_N_PROG_ENABLE REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
81
#define AUD_CONFIG_DISABLE_NCTS REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
94
#define AUD_M_CTS_M_VALUE_INDEX REG_BIT(21)
sys/dev/pci/drm/i915/display/intel_audio_regs.h
95
#define AUD_M_CTS_M_PROG_ENABLE REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_cmtg_regs.h
19
#define CMTG_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_color_regs.h
202
#define PAL_PREC_SPLIT_MODE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_color_regs.h
203
#define PAL_PREC_AUTO_INCREMENT REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_color_regs.h
229
#define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_color_regs.h
242
#define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_color_regs.h
315
#define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_color_regs.h
316
#define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_color_regs.h
74
#define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */
sys/dev/pci/drm/i915/display/intel_color_regs.h
75
#define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */
sys/dev/pci/drm/i915/display/intel_color_regs.h
76
#define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
110
#define SWING_SEL_UPPER_MASK REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
122
#define LOADGEN_SELECT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
133
#define TX_TRAINING_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
134
#define TAP2_DISABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
135
#define TAP3_DISABLE REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
136
#define CURSOR_PROGRAM REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
137
#define COEFF_POLARITY REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
146
#define O_FUNC_OVRD_EN REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
148
#define O_LDO_BYPASS_CRI REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
159
#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
165
#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
28
#define CL_POWER_DOWN_ENABLE REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
33
#define PG_SEQ_DELAY_OVERRIDE_ENABLE REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
43
#define EDP4K2K_MODE_OVRD_EN REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
44
#define EDP4K2K_MODE_OVRD_OPTIMIZED REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
47
#define ICL_LANE_ENABLE_AUX REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
55
#define COMP_INIT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
70
#define IREFGEN REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_combo_phy_regs.h
91
#define COMMON_KEEPER_EN REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
14
#define ADPA_DAC_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
15
#define ADPA_PIPE_SEL_MASK REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
23
#define ADPA_CRT_HOTPLUG_ENABLE REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
24
#define ADPA_CRT_HOTPLUG_PERIOD_MASK REG_BIT(22)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
27
#define ADPA_CRT_HOTPLUG_WARMUP_MASK REG_BIT(21)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
30
#define ADPA_CRT_HOTPLUG_SAMPLE_MASK REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
38
#define ADPA_CRT_HOTPLUG_VOLREF_MASK REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
41
#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
42
#define ADPA_USE_VGA_HVPOLARITY REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
43
#define ADPA_HSYNC_CNTL_DISABLE REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
44
#define ADPA_VSYNC_CNTL_DISABLE REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
45
#define ADPA_VSYNC_ACTIVE_HIGH REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_crt_regs.h
46
#define ADPA_HSYNC_ACTIVE_HIGH REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
14
#define CURSOR_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
15
#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
29
#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
30
#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
31
#define MCURSOR_ROTATE_180 REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
32
#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
48
#define CURSOR_POS_Y_SIGN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
51
#define CURSOR_POS_X_SIGN REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
67
#define CUR_FBC_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
81
#define CUR_WM_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_cursor_regs.h
82
#define CUR_WM_IGNORE_LINES REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
100
#define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
101
#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
106
#define XELPDP_PORT_REVERSAL REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
107
#define XELPDP_PORT_BUF_IO_SELECT_TBT REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
108
#define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
109
#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
110
#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
111
#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
125
#define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
126
#define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
127
#define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
171
#define XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
188
#define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
189
#define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
190
#define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
191
#define XELPDP_LANE_PCLK_REFCLK_ACK(lane) REG_BIT(28 - ((lane) * 4))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
193
#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
194
#define XELPDP_TBT_CLOCK_ACK REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
215
#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
216
#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
217
#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
218
#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
221
#define TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
264
#define C10_TX0_TX_MPLLB_SEL REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
286
#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
289
#define CONTROL0_MAC_TRANSMIT_LFPS REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
339
#define C20_PHY_TX_DCC_BYPASS REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
351
#define C20_MPLLA_FRACEN REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
352
#define C20_FB_CLK_DIV4_EN REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
361
#define C20_MPLLB_FRACEN REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
364
#define C20_PHY_USE_MPLLB REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
426
#define EDP_ON_TYPEC REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
48
#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
55
#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
68
#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
74
#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
99
#define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1052
#define PS_SCALER_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1053
#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1060
#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1063
#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1072
#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1075
#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1078
#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1079
#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1080
#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1081
#define PS_PWRUP_PROGRESS REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1082
#define PS_V_FILTER_BYPASS REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1083
#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1090
#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1092
#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1094
#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1096
#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1107
#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
114
#define IPS_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
115
#define IPS_FALSE_COLOR REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1203
#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1238
#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1239
#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1240
#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1241
#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1242
#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl-mtl */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1243
#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1244
#define GEN12_PIPEDMC_FLIPQ_DONE REG_BIT(24) /* tgl-adl */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1245
#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1246
#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1247
#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1248
#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1249
#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1250
#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1251
#define MTL_PIPEDMC_FLIPQ_DONE REG_BIT(17) /* mtl */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1252
#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1253
#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1254
#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1255
#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1256
#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1257
#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1258
#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1259
#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1260
#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1261
#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1262
#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1263
#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1264
#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1265
#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1266
#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1267
#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1268
#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1269
#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1270
#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1271
#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1273
REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1274
#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1275
#define GEN8_PIPE_VSYNC REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1276
#define GEN8_PIPE_VBLANK REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1298
#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1305
#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1306
#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1307
#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1308
#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1309
#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1310
#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1311
#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1312
#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1313
#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1314
#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1315
#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1325
#define XELPDP_RM_TIMEOUT REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1326
#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1327
#define GEN8_DE_MISC_GSE REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1328
#define GEN8_DE_EDP_PSR REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1329
#define XELPDP_PMDEMAND_RSP REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1330
#define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1351
#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1358
#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1381
#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1383
#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1385
#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1387
#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1395
#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1396
#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1397
#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1398
#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1399
#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1400
#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1411
#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1418
#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1421
#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1422
#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1423
#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1424
#define IVB_PIPE_C_DISABLE REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1425
#define ILK_HDCP_DISABLE REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1426
#define ILK_eDP_A_DISABLE REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1427
#define HSW_CDCLK_LIMIT REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1428
#define ILK_DESKTOP REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1429
#define HSW_CPU_SSC_ENABLE REG_BIT(21)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1432
#define HSW_REF_CLK_SELECT REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1435
#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1436
#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1437
#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1438
#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1439
#define GLK_CL2_PWR_DOWN REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1440
#define GLK_CL1_PWR_DOWN REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1441
#define GLK_CL0_PWR_DOWN REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1444
#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1445
#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1446
#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1449
#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1470
#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1471
#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1474
#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1475
#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1476
#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1477
#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1478
#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1479
#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1480
#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1481
#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1482
#define DP_FEC_BS_JITTER_WA REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1483
#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1484
#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1485
#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1488
#define DISP_DATA_PARTITION_5_6 REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1489
#define DISP_IPC_ENABLE REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1500
#define BW_BUDDY_DISABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1511
#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1512
#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1515
#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1516
#define DCPR_MASK_LPMODE REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1517
#define DCPR_SEND_RESP_IMM REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1518
#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1521
#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1558
#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1559
#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1560
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1561
#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1562
#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1656
#define SDE_PICAINTERRUPT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1658
#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1659
#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
sys/dev/pci/drm/i915/display/intel_display_regs.h
1660
#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
sys/dev/pci/drm/i915/display/intel_display_regs.h
1994
#define TRANS_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
1995
#define TRANS_STATE_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2017
#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2021
#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2022
#define TRANS_DP_ENH_FRAMING REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2028
#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2029
#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2036
#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2037
#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2038
#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2244
#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2245
#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2252
#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2260
#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2277
#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2278
#define CMTG_SECONDARY_MODE REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2283
#define DISABLE_DPT_CLK_GATING REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2291
#define DP_TP_CTL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2292
#define DP_TP_CTL_FEC_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2293
#define DP_TP_CTL_MODE_MASK REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2296
#define DP_TP_CTL_FORCE_ACT REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2301
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2302
#define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2310
#define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2318
#define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2319
#define DP_TP_STATUS_IDLE_DONE REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2320
#define DP_TP_STATUS_ACT_SENT REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2321
#define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2323
#define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2333
#define DDI_BUF_CTL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2334
#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2335
#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2344
#define DDI_BUF_PORT_REVERSAL REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2348
#define DDI_BUF_IS_IDLE REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2349
#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2350
#define DDI_A_4_LANES REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2355
#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2523
#define CDCLK_SQUASH_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2596
#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2622
#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2653
#define PLL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2654
#define PLL_LOCK REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2655
#define PLL_POWER_ENABLE REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2656
#define PLL_POWER_STATE REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2801
#define DC_STATE_EN_DC3CO REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2802
#define DC_STATE_DC3CO_STATUS REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2803
#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2804
#define HOLD_PHY_PG1_LATCH REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2862
#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2902
#define TCSS_DDI_STATUS_READY REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2903
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2904
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2907
#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2910
#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2915
#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_display_regs.h
2920
#define MTL_DPFC_GATING_DIS REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_display_regs.h
316
#define DG2_DPFC_GATING_DIS REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
319
#define DPCE_GATING_DIS REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_display_regs.h
327
#define CURSOR_GATING_DIS REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_display_regs.h
337
#define PIPEDMC_GATING_DIS REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_display_regs.h
519
#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
sys/dev/pci/drm/i915/display/intel_display_regs.h
520
#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
521
#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_display_regs.h
622
#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_display_regs.h
635
#define DP_PORT_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
665
#define DP_ENHANCED_FRAMING REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_display_regs.h
669
#define DP_PORT_REVERSAL REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_display_regs.h
670
#define EDP_PLL_ENABLE REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_display_regs.h
671
#define DP_CLOCK_OUTPUT_ENABLE REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_display_regs.h
672
#define DP_SCRAMBLING_DISABLE REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_display_regs.h
673
#define DP_SCRAMBLING_DISABLE_ILK REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_display_regs.h
674
#define DP_COLOR_RANGE_16_235 REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_display_regs.h
675
#define DP_AUDIO_OUTPUT_ENABLE REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_display_regs.h
676
#define DP_SYNC_VS_HIGH REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
677
#define DP_SYNC_HS_HIGH REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_display_regs.h
678
#define DP_DETECTED REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_display_regs.h
727
#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
732
#define TRANSCONF_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_display_regs.h
733
#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
sys/dev/pci/drm/i915/display/intel_display_regs.h
734
#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
735
#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
sys/dev/pci/drm/i915/display/intel_display_regs.h
738
#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_display_regs.h
739
#define TRANSCONF_FORCE_BORDER REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_display_regs.h
740
#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
sys/dev/pci/drm/i915/display/intel_display_regs.h
764
#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_display_regs.h
767
#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_display_regs.h
768
#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
sys/dev/pci/drm/i915/display/intel_display_regs.h
769
#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_display_regs.h
770
#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_display_regs.h
775
#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
sys/dev/pci/drm/i915/display/intel_display_regs.h
781
#define TRANSCONF_DITHER_EN REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
843
#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_display_regs.h
848
#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
849
#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
850
#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
851
#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
sys/dev/pci/drm/i915/display/intel_display_regs.h
852
#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
sys/dev/pci/drm/i915/display/intel_display_regs.h
853
#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
854
#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
sys/dev/pci/drm/i915/display/intel_display_regs.h
855
#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_display_regs.h
856
#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_display_regs.h
857
#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
sys/dev/pci/drm/i915/display/intel_display_regs.h
869
#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
888
#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_display_regs.h
889
#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_display_regs.h
890
#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_display_regs.h
891
#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_display_regs.h
892
#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_display_regs.h
893
#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
sys/dev/pci/drm/i915/display/intel_display_regs.h
894
#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
sys/dev/pci/drm/i915/display/intel_display_regs.h
895
#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_display_regs.h
896
#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_display_regs.h
897
#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_display_regs.h
898
#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_display_regs.h
899
#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_display_regs.h
902
#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_display_regs.h
903
#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_display_regs.h
904
#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
sys/dev/pci/drm/i915/display/intel_display_regs.h
905
#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_display_regs.h
906
#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_display_regs.h
907
#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_display_regs.h
908
#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
sys/dev/pci/drm/i915/display/intel_display_regs.h
909
#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_display_regs.h
910
#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_display_regs.h
911
#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_display_regs.h
912
#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_display_regs.h
913
#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
151
#define DKL_TX_DP20BITMODE REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
156
#define LOADGEN_SHARING_PMD_DISABLE REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
56
#define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
285
#define PIPEDMC_ENABLE REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
288
#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
297
#define PIPEDMC_HALT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
298
#define PIPEDMC_STEP REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
299
#define PIPEDMC_CLOCKGATE REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
315
#define PIPEDMC_FQ_CTRL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
316
#define PIPEDMC_FQ_CTRL_ASYNC REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
317
#define PIPEDMC_FQ_CTRL_PREEMPT REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
322
#define PIPEDMC_FQ_STATUS_BUSY REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
323
#define PIPEDMC_FQ_STATUS_W2_LIVE_STATUS REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
324
#define PIPEDMC_FQ_STATUS_W1_LIVE_STATUS REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
351
#define PIPEDMC_SCANLINECMP_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
357
#define PIPEDMC_SCANLINEINRANGECMP_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
358
#define PIPEDMC_SCANLINEOUTRANGECMP_EN REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
436
#define PIPEDMC_SW_DMC_WAKE REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
441
#define PIPEDMC_DMC_INT_AT_DELAYED_VBLANK REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
442
#define PIPEDMC_W1_DMC_WAKE REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
450
#define PIPEDMC_FLIPQ_PROG_DONE REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
451
#define PIPEDMC_ERROR REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
452
#define PIPEDMC_GTT_FAULT REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
453
#define PIPEDMC_ATS_FAULT REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
492
#define DMC_EVT_CTL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
493
#define DMC_EVT_CTL_RECURRING REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
535
#define DMC_WAKELOCK_CFG_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
537
#define DMC_WAKELOCK_CTL_REQ REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
538
#define DMC_WAKELOCK_CTL_ACK REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
556
#define LNL_FQ_INTERRUPT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
559
#define LNL_FQ_EXECUTED REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
571
#define PTL_FQ_INTERRUPT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
572
#define PTL_FQ_NEED_PUSH REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
573
#define PTL_FQ_BLOCK_PUSH REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
574
#define PTL_FQ_EXECUTED REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
103
#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
104
#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
46
#define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
47
#define DP_AUX_CH_CTL_DONE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
48
#define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
49
#define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
55
#define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
60
#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) /* mtl+ */
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
61
#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) /* mtl+ */
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
62
#define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
63
#define DP_AUX_CH_CTL_MANCHESTER_TEST REG_BIT(14) /* pre-hsw */
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
64
#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL REG_BIT(14) /* skl+ */
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
65
#define DP_AUX_CH_CTL_SYNC_TEST REG_BIT(13) /* pre-hsw */
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
66
#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL REG_BIT(13) /* skl+ */
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
67
#define DP_AUX_CH_CTL_DEGLITCH_TEST REG_BIT(12) /* pre-hsw */
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
68
#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL REG_BIT(12) /* skl+ */
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
69
#define DP_AUX_CH_CTL_PRECHARGE_TEST REG_BIT(11) /* pre-hsw */
sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h
70
#define DP_AUX_CH_CTL_TBT_IO REG_BIT(11) /* icl+ */
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
18
#define DSB_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
19
#define DSB_BUF_REITERATE REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
20
#define DSB_WAIT_FOR_VBLANK REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
21
#define DSB_WAIT_FOR_LINE_IN REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
22
#define DSB_HALT REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
23
#define DSB_NON_POSTED REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
24
#define DSB_STATUS_BUSY REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
26
#define DSB_MMIO_DEAD_CLOCKS_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
32
#define DSB_POLL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
40
#define DSB_HP_IDLE_STATUS REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
41
#define DSB_DEWAKE_STATUS REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
43
#define DSB_SAFE_WINDOW_LIVE REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
46
#define DSB_SAFE_WINDOW REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
48
#define DSB_BUSY_DURING_DELAYED_VBLANK REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
54
#define DSB_GOSUB_INT_EN REG_BIT(21) /* ptl+ */
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
55
#define DSB_ATS_FAULT_INT_EN REG_BIT(20) /* mtl+ */
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
56
#define DSB_GTT_FAULT_INT_EN REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
57
#define DSB_RSPTIMEOUT_INT_EN REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
58
#define DSB_POLL_ERR_INT_EN REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
59
#define DSB_PROG_INT_EN REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
60
#define DSB_GOSUB_INT_STATUS REG_BIT(5) /* ptl+ */
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
61
#define DSB_ATS_FAULT_INT_STATUS REG_BIT(4) /* mtl+ */
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
62
#define DSB_GTT_FAULT_INT_STATUS REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
63
#define DSB_RSPTIMEOUT_INT_STATUS REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
64
#define DSB_POLL_ERR_INT_STATUS REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
65
#define DSB_PROG_INT_STATUS REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
68
#define DSB_RM_CLAIM_TIMEOUT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
69
#define DSB_RM_READY_TIMEOUT REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
76
#define DSB_ENABLE_DEWAKE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
80
#define DSB_MMIOGEN_DEWAKE_DIS REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
81
#define DSB_FORCE_DEWAKE REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
82
#define DSB_BLOCK_DEWAKE_EXTENSION REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
83
#define DSB_OVERRIDE_DC5_DC6_OK REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
88
#define DSB_FORCE_DMA_SYNC_RESET REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
89
#define DSB_FORCE_VTD_ENGIE_RESET REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
90
#define DSB_DISABLE_IPC_DEMOTE REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
91
#define DSB_SKIP_WAITS_EN REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
92
#define DSB_EXTEND_HP_IDLE REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
93
#define DSB_CTRL_WAIT_SAFE_WINDOW REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
94
#define DSB_CTRL_NO_WAIT_VBLANK REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
95
#define DSB_INST_WAIT_SAFE_WINDOW REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
96
#define DSB_INST_NO_WAIT_VBLANK REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
97
#define DSB_MMIOGEN_DEWAKE_DIS_CHICKEN REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_dsb_regs.h
98
#define DSB_DISABLE_MMIO_COUNT_FOR_INDEXED REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
15
#define DVO_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
16
#define DVO_PIPE_SEL_MASK REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
22
#define DVO_INTERRUPT_SELECT REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
23
#define DVO_DEDICATED_INT_ENABLE REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
25
#define DVO_USE_VGA_SYNC REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
26
#define DVO_DATA_ORDER_MASK REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
29
#define DVO_VSYNC_DISABLE REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
30
#define DVO_HSYNC_DISABLE REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
31
#define DVO_VSYNC_TRISTATE REG_BIT(9)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
32
#define DVO_HSYNC_TRISTATE REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
33
#define DVO_BORDER_ENABLE REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
34
#define DVO_ACT_DATA_ORDER_MASK REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
39
#define DVO_VSYNC_ACTIVE_HIGH REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
40
#define DVO_HSYNC_ACTIVE_HIGH REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
41
#define DVO_BLANK_ACTIVE_HIGH REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
42
#define DVO_OUTPUT_CSTATE_PIXELS REG_BIT(1) /* SDG only */
sys/dev/pci/drm/i915/display/intel_dvo_regs.h
43
#define DVO_OUTPUT_SOURCE_SIZE_PIXELS REG_BIT(0) /* SDG only */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
110
#define FBC_DIRTY_RECT_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
113
#define ILK_FBC_RT_VALID REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
114
#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
117
#define SNB_DPFC_FENCE_EN REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
12
#define FBC_CTL_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
126
#define FBC_REND_NUKE REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
127
#define FBC_REND_CACHE_CLEAN REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
13
#define FBC_CTL_PERIODIC REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
16
#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
17
#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
18
#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
24
#define FBC_CMD_COMPRESS REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
26
#define FBC_STAT_COMPRESSING REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
27
#define FBC_STAT_COMPRESSED REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
28
#define FBC_STAT_MODIFIED REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
31
#define FBC_CTL_FENCE_DBL REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
37
#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
43
#define FBC_MOD_NUM_VALID REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
57
#define DPFC_CTL_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
58
#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
60
#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
63
#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
64
#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
67
#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
68
#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
69
#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
78
#define DPFC_RECOMP_STALL_EN REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
92
#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
93
#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
94
#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
95
#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
96
#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
99
#define FBC_STRIDE_OVERRIDE REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
15
#define HDCP_AKSV_SEND_TRIGGER REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
16
#define HDCP_CLEAR_KEYS_TRIGGER REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
168
#define HDCP_STATUS_STREAM_A_ENC REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
169
#define HDCP_STATUS_STREAM_B_ENC REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
17
#define HDCP_KEY_LOAD_TRIGGER REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
170
#define HDCP_STATUS_STREAM_C_ENC REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
171
#define HDCP_STATUS_STREAM_D_ENC REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
172
#define HDCP_STATUS_AUTH REG_BIT(21)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
173
#define HDCP_STATUS_ENC REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
174
#define HDCP_STATUS_RI_MATCH REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
175
#define HDCP_STATUS_R0_READY REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
176
#define HDCP_STATUS_AN_READY REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
177
#define HDCP_STATUS_CIPHER REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
19
#define HDCP_FUSE_IN_PROGRESS REG_BIT(7)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
20
#define HDCP_FUSE_ERROR REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
200
#define AUTH_LINK_AUTHENTICATED REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
201
#define AUTH_LINK_TYPE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
202
#define AUTH_FORCE_CLR_INPUTCTR REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
203
#define AUTH_CLR_KEYS REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
21
#define HDCP_FUSE_DONE REG_BIT(5)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
214
#define CTL_LINK_ENCRYPTION_REQ REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
22
#define HDCP_KEY_LOAD_STATUS REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
226
#define LINK_TYPE_STATUS REG_BIT(22)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
227
#define LINK_AUTH_STATUS REG_BIT(21)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
228
#define LINK_ENCRYPTION_STATUS REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
23
#define HDCP_KEY_LOAD_DONE REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
249
#define STREAM_ENCRYPTION_STATUS REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
29
#define HDCP_TRANSA_REP_PRESENT REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
30
#define HDCP_TRANSB_REP_PRESENT REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
31
#define HDCP_TRANSC_REP_PRESENT REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
32
#define HDCP_TRANSD_REP_PRESENT REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
33
#define HDCP_DDIB_REP_PRESENT REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
34
#define HDCP_DDIA_REP_PRESENT REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
35
#define HDCP_DDIC_REP_PRESENT REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
36
#define HDCP_DDID_REP_PRESENT REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
37
#define HDCP_DDIF_REP_PRESENT REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
38
#define HDCP_DDIE_REP_PRESENT REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
49
#define HDCP_SHA1_BUSY REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
50
#define HDCP_SHA1_READY REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
51
#define HDCP_SHA1_COMPLETE REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
52
#define HDCP_SHA1_V_MATCH REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
91
#define HDCP_CONF_CAPTURE_AN REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_hdcp_regs.h
92
#define HDCP_CONF_AUTH_AND_ENC (REG_BIT(1) | REG_BIT(0))
sys/dev/pci/drm/i915/display/intel_hti_regs.h
13
#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
sys/dev/pci/drm/i915/display/intel_hti_regs.h
14
#define HDPORT_ENABLED REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_lvds_regs.h
17
#define LVDS_PORT_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_lvds_regs.h
19
#define LVDS_PIPE_SEL_MASK REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_lvds_regs.h
24
#define LVDS_ENABLE_DITHER REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_lvds_regs.h
26
#define LVDS_VSYNC_POLARITY REG_BIT(21)
sys/dev/pci/drm/i915/display/intel_lvds_regs.h
27
#define LVDS_HSYNC_POLARITY REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_lvds_regs.h
30
#define LVDS_BORDER_ENABLE REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_lvds_regs.h
63
#define LVDS_DETECTED REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_pfit_regs.h
11
#define PFIT_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_pfit_regs.h
25
#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
sys/dev/pci/drm/i915/display/intel_pfit_regs.h
28
#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
sys/dev/pci/drm/i915/display/intel_pfit_regs.h
29
#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
sys/dev/pci/drm/i915/display/intel_pfit_regs.h
46
#define PF_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
103
#define PIPE_CRC_EXP_3_MASK_IVB REG_BIT(22, 0) /* ivb */
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
109
#define PIPE_CRC_EXP_4_MASK_IVB REG_BIT(22, 0) /* ivb */
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
115
#define PIPE_CRC_EXP_5_MASK_IVB REG_BIT(22, 0) /* ivb */
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
13
#define PIPE_CRC_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
58
#define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
59
#define PIPE_CRC_EXP_RED_MASK REG_BIT(22, 0) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
60
#define PIPE_CRC_EXP_1_MASK_IVB REG_BIT(22, 0) /* ivb */
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
64
#define PIPE_CRC_EXP_GREEN_MASK REG_BIT(22, 0) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
68
#define PIPE_CRC_EXP_BLUE_MASK REG_BIT(22, 0) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
72
#define PIPE_CRC_EXP_RES1_MASK REG_BIT(22, 0) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
76
#define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h
97
#define PIPE_CRC_EXP_2_MASK_IVB REG_BIT(22, 0) /* ivb */
sys/dev/pci/drm/i915/display/intel_pps_regs.h
21
#define PP_ON REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_pps_regs.h
29
#define PP_READY REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_pps_regs.h
34
#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_pps_regs.h
51
#define EDP_FORCE_VDD REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_pps_regs.h
52
#define EDP_BLC_ENABLE REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_pps_regs.h
53
#define PANEL_POWER_RESET REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_pps_regs.h
54
#define PANEL_POWER_ON REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
120
#define EDP_PSR_STATUS_AUX_ERROR REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
121
#define EDP_PSR_STATUS_AUX_SENDING REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
122
#define EDP_PSR_STATUS_SENDING_IDLE REG_BIT(9)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
123
#define EDP_PSR_STATUS_SENDING_TP2_TP3 REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
124
#define EDP_PSR_STATUS_SENDING_TP1 REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
138
#define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
139
#define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
14
#define EXITLINE_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
140
#define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
141
#define EDP_PSR_DEBUG_MASK_HPD REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
142
#define EDP_PSR_DEBUG_MASK_FBC_MODIFY REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
143
#define EDP_PSR_DEBUG_MASK_PRIMARY_FLIP REG_BIT(23) /* hsw */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
144
#define EDP_PSR_DEBUG_MASK_HDCP_ENABLE REG_BIT(22) /* hsw/bdw */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
145
#define EDP_PSR_DEBUG_MASK_SPRITE_ENABLE REG_BIT(21) /* hsw */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
146
#define EDP_PSR_DEBUG_MASK_CURSOR_MOVE REG_BIT(20) /* hsw */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
147
#define EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT REG_BIT(19) /* hsw */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
148
#define EDP_PSR_DEBUG_MASK_DPST_PHASE_IN REG_BIT(18) /* hsw */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
149
#define EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
150
#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE REG_BIT(16) /* hsw-skl */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
151
#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN REG_BIT(15) /* skl+ */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
152
#define EDP_PSR_DEBUG_RFB_UPDATE_SENT REG_BIT(2) /* bdw */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
153
#define EDP_PSR_DEBUG_ENTRY_COMPLETION REG_BIT(1) /* hsw/bdw */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
158
#define EDP_PSR2_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
159
#define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
160
#define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
163
#define LNL_EDP_PSR2_SU_REGION_ET_ENABLE REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
164
#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
165
#define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
204
#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
205
#define PSR_EVENT_PSR2_DISABLED REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
206
#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
207
#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
208
#define PSR_EVENT_GRAPHICS_RESET REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
209
#define PSR_EVENT_PCH_INTERRUPT REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
210
#define PSR_EVENT_MEMORY_UP REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
211
#define PSR_EVENT_FRONT_BUFFER_MODIFY REG_BIT(9)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
212
#define PSR_EVENT_WD_TIMER_EXPIRE REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
213
#define PSR_EVENT_PIPE_REGISTERS_UPDATE REG_BIT(6)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
214
#define PSR_EVENT_REGISTER_UPDATE REG_BIT(5) /* Reserved in ICL+ */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
215
#define PSR_EVENT_HDCP_ENABLE REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
216
#define PSR_EVENT_KVMR_SESSION_ENABLE REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
217
#define PSR_EVENT_VBI_ENABLE REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
218
#define PSR_EVENT_LPSP_MODE_EXIT REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
219
#define PSR_EVENT_PSR_DISABLE REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
238
#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
243
#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
244
#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
245
#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
250
#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
251
#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
252
#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
257
#define LNL_SFF_CTL_SF_SINGLE_FULL_FRAME REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
262
#define LNL_CFF_CTL_SF_CONTINUOUS_FULL_FRAME REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
28
#define EDP_PSR_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
281
#define ALPM_CTL_ALPM_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
282
#define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
283
#define ALPM_CTL_LOBF_ENABLE REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
284
#define ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
285
#define ALPM_CTL_KEEP_FEC_ENABLE_FOR_AUX_WAKE_SLEEP REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
286
#define ALPM_CTL_RESTORE_OCCURED REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
287
#define ALPM_CTL_RESTORE_TO_SLEEP REG_BIT(25)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
288
#define ALPM_CTL_RESTORE_TO_DEEP_SLEEP REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
29
#define BDW_PSR_SINGLE_FRAME REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
294
#define ALPM_CTL_AUX_WAKE_SLEEP_HOLD_ENABLE REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
30
#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
31
#define EDP_PSR_LINK_STANDBY REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
313
#define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR REG_BIT(4)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
320
#define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
331
#define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
41
#define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
42
#define EDP_PSR_TP_MASK REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
45
#define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */
sys/dev/pci/drm/i915/display/intel_psr_regs.h
75
#define TGL_PSR_ERROR REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
76
#define TGL_PSR_POST_EXIT REG_BIT(1)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
77
#define TGL_PSR_PRE_ENTRY REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
94
#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT REG_BIT(11)
sys/dev/pci/drm/i915/display/intel_sbi_regs.h
28
#define SBI_CTL_OP_WR REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
29
#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
30
#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
31
#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
35
#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
36
#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
37
#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
39
#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
42
#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
43
#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
51
#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
52
#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
100
#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
101
#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
119
#define SPRITE_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
120
#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
121
#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
129
#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
13
#define DVS_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
130
#define SPRITE_SOURCE_KEY REG_BIT(22)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
131
#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
132
#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
133
#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
139
#define SPRITE_ROTATE_180 REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
14
#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
140
#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
141
#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
142
#define SPRITE_TILED REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
143
#define SPRITE_DEST_KEY REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
15
#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
205
#define SPRITE_SCALE_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
21
#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
210
#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
211
#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
22
#define DVS_SOURCE_KEY REG_BIT(22)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
23
#define DVS_RGB_ORDER_XBGR REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
238
#define SP_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
239
#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
24
#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
252
#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
253
#define SP_SOURCE_KEY REG_BIT(22)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
254
#define SP_YUV_FORMAT_BT709 REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
260
#define SP_ROTATE_180 REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
261
#define SP_TILED REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
262
#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
30
#define DVS_ROTATE_180 REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
31
#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
316
#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
32
#define DVS_TILED REG_BIT(10)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
33
#define DVS_DEST_KEY REG_BIT(2)
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
95
#define DVS_SCALE_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
24
#define VDSC0_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
25
#define VDSC2_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
26
#define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
27
#define VDSC1_ENABLE REG_BIT(15)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
42
#define ULTRA_JOINER_ENABLE REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
43
#define PRIMARY_ULTRA_JOINER_ENABLE REG_BIT(22)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
86
#define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
87
#define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
88
#define DSC_PPS0_ALT_ICH_SEL REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
89
#define DSC_PPS0_VBR_ENABLE REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
90
#define DSC_PPS0_422_ENABLE REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
91
#define DSC_PPS0_COLOR_SPACE_CONVERSION REG_BIT(17)
sys/dev/pci/drm/i915/display/intel_vdsc_regs.h
92
#define DSC_PPS0_BLOCK_PREDICTION REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_vga_regs.h
14
#define VGA_DISP_DISABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_vga_regs.h
15
#define VGA_2X_MODE REG_BIT(30) /* pre-ilk */
sys/dev/pci/drm/i915/display/intel_vga_regs.h
16
#define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_vga_regs.h
20
#define VGA_BORDER_ENABLE REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_vga_regs.h
21
#define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
sys/dev/pci/drm/i915/display/intel_vga_regs.h
23
#define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_vga_regs.h
24
#define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_vga_regs.h
25
#define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */
sys/dev/pci/drm/i915/display/intel_vga_regs.h
26
#define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20)
sys/dev/pci/drm/i915/display/intel_vga_regs.h
27
#define VGA_PALETTE_BYPASS REG_BIT(19)
sys/dev/pci/drm/i915/display/intel_vga_regs.h
28
#define VGA_NINE_DOT_DISABLE REG_BIT(18)
sys/dev/pci/drm/i915/display/intel_vga_regs.h
29
#define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */
sys/dev/pci/drm/i915/display/intel_vga_regs.h
30
#define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
16
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
17
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
18
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
19
#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
22
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
46
#define VRR_VMAXSHIFT_DEC REG_BIT(16)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
54
#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
55
#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
56
#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
57
#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
58
#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
59
#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
74
#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
75
#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
76
#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
98
#define TRANS_PUSH_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/intel_vrr_regs.h
99
#define TRANS_PUSH_SEND REG_BIT(30)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
151
#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
161
#define PLANE_SURF_DECRYPT REG_BIT(2)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
162
#define PLANE_SURF_ASYNC_UPDATE REG_BIT(0)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
228
#define PLANE_CUS_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
229
#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
234
#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
239
#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
252
#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
253
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
254
#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
255
#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
256
#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
263
#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
323
#define PLANE_WM_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
324
#define PLANE_WM_IGNORE_LINES REG_BIT(30)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
325
#define PLANE_WM_AUTO_MIN_ALLOC_EN REG_BIT(29)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
360
#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
38
#define PLANE_CTL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
391
#define PLANE_AUTO_MIN_DBUF_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
41
#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
411
#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
42
#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
67
#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
71
#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
72
#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
73
#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
79
#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
80
#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
81
#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
82
#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
89
#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
90
#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
91
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
sys/dev/pci/drm/i915/display/skl_watermark_regs.h
19
#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
sys/dev/pci/drm/i915/display/skl_watermark_regs.h
36
#define MBUS_JOIN REG_BIT(31)
sys/dev/pci/drm/i915/display/skl_watermark_regs.h
37
#define MBUS_HASHING_MODE_MASK REG_BIT(30)
sys/dev/pci/drm/i915/display/skl_watermark_regs.h
63
#define DBUF_POWER_REQUEST REG_BIT(31)
sys/dev/pci/drm/i915/display/skl_watermark_regs.h
64
#define DBUF_POWER_STATE REG_BIT(30)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
111
#define DPIO_PCS_SWING_CALC_TX1_TX3 REG_BIT(31)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
112
#define DPIO_PCS_SWING_CALC_TX0_TX2 REG_BIT(30)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
125
#define DPIO_LANEDESKEW_STRAP_OVRD REG_BIT(3)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
126
#define DPIO_LEFT_TXFIFO_RST_MASTER REG_BIT(1)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
127
#define DPIO_RIGHT_TXFIFO_RST_MASTER REG_BIT(0)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
138
#define DPIO_LANESTAGGER_STRAP_OVRD REG_BIT(6)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
165
#define DPIO_TX_UNIQ_TRANS_SCALE_EN REG_BIT(27)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
178
#define DPIO_TX_OCALINIT_EN REG_BIT(31)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
203
#define DPIO_CHV_FRAC_DIV_EN REG_BIT(16)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
204
#define DPIO_CHV_SECOND_MOD REG_BIT(8)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
223
#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE REG_BIT(0) /* 1: coarse & 0 : fine */
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
226
#define DPIO_ALLDL_POWERDOWN_CH0 REG_BIT(19)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
227
#define DPIO_ANYDL_POWERDOWN_CH0 REG_BIT(18)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
251
#define DPIO_PLL_FREQLOCK REG_BIT(1)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
252
#define DPIO_PLL_LOCK REG_BIT(0)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
257
#define DPIO_AFC_RECAL REG_BIT(14)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
258
#define DPIO_DCLKP_EN REG_BIT(13)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
271
#define DPIO_ALLDL_POWERDOWN_CH1 REG_BIT(30) /* CL2 DW6 only */
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
272
#define DPIO_ANYDL_POWERDOWN_CH1 REG_BIT(29) /* CL2 DW6 only */
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
273
#define DPIO_DYNPWRDOWNEN_CH1 REG_BIT(28) /* CL2 DW6 only */
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
274
#define CHV_CMN_USEDCLKCHANNEL REG_BIT(13)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
278
#define DPIO_CL1POWERDOWNEN REG_BIT(23)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
279
#define DPIO_DYNPWRDOWNEN_CH0 REG_BIT(22)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
287
#define DPIO_CL2_LDOFUSE_PWRENB REG_BIT(6)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
288
#define DPIO_LRC_BYPASS REG_BIT(3)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
307
#define DPIO_UPAR REG_BIT(30)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
41
#define DPIO_ENABLE_CALIBRATION REG_BIT(11)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
48
#define DPIO_REFSEL_OVERRIDE REG_BIT(27)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
75
#define DPIO_PCS_TX_LANE2_RESET REG_BIT(16)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
76
#define DPIO_PCS_TX_LANE1_RESET REG_BIT(7)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
77
#define DPIO_LEFT_TXFIFO_RST_MASTER2 REG_BIT(4)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
78
#define DPIO_RIGHT_TXFIFO_RST_MASTER2 REG_BIT(3)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
83
#define CHV_PCS_REQ_SOFTRESET_EN REG_BIT(23)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
84
#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN REG_BIT(22)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
85
#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
90
#define DPIO_PCS_CLK_SOFT_RESET REG_BIT(5)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
95
#define DPIO_PCS_USEDCLKCHANNEL REG_BIT(21)
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
96
#define DPIO_PCS_USEDCLKCHANNEL_OVRRIDE REG_BIT(20)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
104
#define RESET_CTL_CAT_ERROR REG_BIT(2)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
105
#define RESET_CTL_READY_TO_RESET REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
106
#define RESET_CTL_REQUEST_RESET REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
130
#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
131
#define ECO_GATING_CX_ONLY REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
132
#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
133
#define ECO_FLIP_DONE REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
182
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
183
#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
184
#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
185
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
186
#define GEN12_CTX_CTRL_RUNALONE_MODE REG_BIT(7)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
187
#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
199
#define GEN12_GFX_PREFETCH_DISABLE REG_BIT(10)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
214
#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
235
#define EL_CTRL_LOAD REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
257
#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
258
#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
261
#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
264
#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
267
#define MFXPIPE_CLKGATE_DIS REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
48
#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
49
#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
50
#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
51
#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
52
#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
53
#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
54
#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
74
#define ASYNC_FLIP_PERF_DISABLE REG_BIT(14)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
75
#define MI_FLUSH_ENABLE REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
76
#define TGL_NESTED_BB_EN REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
77
#define MODE_IDLE REG_BIT(9)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
78
#define STOP_RING REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_engine_regs.h
79
#define VS_TIMER_DISPATCH REG_BIT(6)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
137
#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
157
#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
158
#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
179
#define MI_LRR_SOURCE_CS_MMIO REG_BIT(18)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
189
#define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
190
#define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
258
#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
259
#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
310
#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
375
#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
376
#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG REG_BIT(9)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
400
#define MI_DO_COMPARE REG_BIT(21)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
404
#define BASE_ADDRESS_MODIFY REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gpu_commands.h
407
#define PIPELINE_SELECT_MEDIA REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1011
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1064
#define FORCE_MISS_FTLB REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1067
#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1068
#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1069
#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1072
#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1073
#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1104
#define ENABLE_SMALLPL REG_BIT(15)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1105
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1106
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1107
#define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1108
#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1111
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1112
#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1113
#define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1114
#define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1117
#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1118
#define DISABLE_ECC REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1119
#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1125
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1126
#define DISABLE_PREFETCH_INTO_IC REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1132
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1133
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1134
#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1135
#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1142
#define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1145
#define FLOW_CONTROL_ENABLE REG_BIT(15)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1146
#define UGM_BACKUP_MODE REG_BIT(13)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1147
#define MDQ_ARBITRATION_MODE REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1148
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1149
#define STALL_DOP_GATING_DISABLE REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1151
#define DISABLE_EARLY_EOT REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1156
#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1157
#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1158
#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1159
#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1160
#define XELPG_DISABLE_TDL_SVHS_GATING REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1161
#define GEN12_DISABLE_DOP_GATING REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1164
#define DIS_NULL_QUERY REG_BIT(10)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1173
#define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1182
#define DISABLE_D8_D16_COASLESCE REG_BIT(30)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1183
#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1185
#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1186
#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1187
#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1188
#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1190
#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1423
#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1424
#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1436
#define CHV_FGT_DISABLE_SS1 REG_BIT(11)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1437
#define CHV_FGT_DISABLE_SS0 REG_BIT(10)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1440
#define BCS_SRC_Y REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
1441
#define BCS_DST_Y REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
165
#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
173
#define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
176
#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
178
#define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
242
#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
328
#define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
331
#define RING_FAULT_VALID REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
356
#define AUX_INV REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
38
#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
391
#define FAULT_GTT_SEL REG_BIT(4)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
418
#define WAIT_ON_DEPTH_STALL_DONE_DISABLE REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
426
#define TBIMR_FAST_CLIP REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
429
#define VF_PREFETCH_TLB_DIS REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
430
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
431
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
443
#define DISABLE_REPACKING_FOR_COMPRESSION REG_BIT(15) /* jsl+ */
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
447
#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
448
#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
449
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
450
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
468
#define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
469
#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
470
#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
471
#define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
479
#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
482
#define FD_END_COLLECT REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
498
#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
504
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
505
#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
506
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
507
#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
511
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
515
#define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
516
#define GEN9_PGCTL_SLICE_ACK REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
528
#define GEN9_PGCTL_SSB_EU311_ACK REG_BIT(14)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
529
#define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
530
#define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
531
#define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
532
#define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
533
#define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
534
#define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
535
#define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
541
#define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
546
#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
547
#define GEN12_SQCNT1_OABPC REG_BIT(29)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
548
#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
551
#define EN_32B_ACCESS REG_BIT(30)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
575
#define FBC_LLC_FULLY_OPEN REG_BIT(30)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
674
#define XEHPC_GRDOM_BLT8 REG_BIT(31)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
675
#define XEHPC_GRDOM_BLT7 REG_BIT(30)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
676
#define XEHPC_GRDOM_BLT6 REG_BIT(29)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
677
#define XEHPC_GRDOM_BLT5 REG_BIT(28)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
678
#define XEHPC_GRDOM_BLT4 REG_BIT(27)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
679
#define XEHPC_GRDOM_BLT3 REG_BIT(26)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
680
#define XEHPC_GRDOM_BLT2 REG_BIT(25)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
681
#define XEHPC_GRDOM_BLT1 REG_BIT(24)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
682
#define GEN12_GRDOM_GSC REG_BIT(21)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
683
#define GEN11_GRDOM_SFC3 REG_BIT(20)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
684
#define GEN11_GRDOM_SFC2 REG_BIT(19)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
685
#define GEN11_GRDOM_SFC1 REG_BIT(18)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
686
#define GEN11_GRDOM_SFC0 REG_BIT(17)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
687
#define GEN11_GRDOM_VECS4 REG_BIT(16)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
688
#define GEN11_GRDOM_VECS3 REG_BIT(15)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
689
#define GEN11_GRDOM_VECS2 REG_BIT(14)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
690
#define GEN11_GRDOM_VECS REG_BIT(13)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
691
#define GEN11_GRDOM_MEDIA8 REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
692
#define GEN11_GRDOM_MEDIA7 REG_BIT(11)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
693
#define GEN11_GRDOM_MEDIA6 REG_BIT(10)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
694
#define GEN11_GRDOM_MEDIA5 REG_BIT(9)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
695
#define GEN11_GRDOM_MEDIA4 REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
696
#define GEN11_GRDOM_MEDIA3 REG_BIT(7)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
697
#define GEN11_GRDOM_MEDIA2 REG_BIT(6)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
698
#define GEN11_GRDOM_MEDIA REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
699
#define GEN11_GRDOM_GUC REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
700
#define GEN11_GRDOM_BLT REG_BIT(2)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
707
#define GEN7_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
708
#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
719
#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
722
#define VFUNIT_CLKGATE_DIS REG_BIT(20)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
723
#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
724
#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
725
#define HSUNIT_CLKGATE_DIS REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
726
#define VSUNIT_CLKGATE_DIS REG_BIT(3)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
733
#define NODEDSS_CLKGATE_DIS REG_BIT(12)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
734
#define L3_CLKGATE_DIS REG_BIT(16)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
735
#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
738
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
739
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
742
#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
743
#define GWUNIT_CLKGATE_DIS REG_BIT(16)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
746
#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
749
#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
75
#define GEN11_MCR_MULTICAST REG_BIT(31)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
781
#define GEN12_MEDIA_FREQ_RATIO REG_BIT(13)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
870
#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
871
#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
872
#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
873
#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
874
#define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
883
#define CTC_SOURCE_PARAMETER_MASK REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
906
#define IDLE_MSG_DISABLE REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
929
#define CHV_EU210_PG_ENABLE REG_BIT(25)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
930
#define CHV_EU19_PG_ENABLE REG_BIT(17)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
931
#define CHV_EU08_PG_ENABLE REG_BIT(9)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
932
#define CHV_SS_PG_ENABLE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
934
#define CHV_EU311_PG_ENABLE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
942
#define GEN12_BUS_HASH_CTL_BIT_EXC REG_BIT(7)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
943
#define GEN9_GAPS_TSV_CREDIT_DISABLE REG_BIT(7)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
948
#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
979
#define XEHP_LNESPARE REG_BIT(19)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
996
#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
999
#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
sys/dev/pci/drm/i915/gt/intel_gtt.h
140
#define CHV_PPAT_SNOOP REG_BIT(6)
sys/dev/pci/drm/i915/gt/intel_gtt.h
77
#define GEN6_PTE_VALID REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gtt.h
83
#define GEN6_PDE_VALID REG_BIT(0)
sys/dev/pci/drm/i915/gt/intel_gtt.h
88
#define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
sys/dev/pci/drm/i915/gt/intel_gtt.h
89
#define BYT_PTE_WRITEABLE REG_BIT(1)
sys/dev/pci/drm/i915/gt/intel_migrate.c
411
*cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */
sys/dev/pci/drm/i915/gt/intel_migrate.c
444
*cs++ = MI_STORE_DATA_IMM | REG_BIT(21);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
967
poison &= ~REG_BIT(0);
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_abi.h
188
#define INTEL_GUC_TLB_INVAL_FLUSH_CACHE REG_BIT(31)
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
156
#define SLPC_GTPERF_TASK_ENABLED REG_BIT(0)
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
157
#define SLPC_DCC_TASK_ENABLED REG_BIT(11)
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
158
#define SLPC_IN_DCC REG_BIT(12)
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
159
#define SLPC_BALANCER_ENABLED REG_BIT(15)
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
160
#define SLPC_IBC_TASK_ENABLED REG_BIT(16)
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
161
#define SLPC_BALANCER_IA_LMT_ENABLED REG_BIT(17)
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
162
#define SLPC_BALANCER_IA_LMT_ACTIVE REG_BIT(18)
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
219
#define SLPC_CTX_FREQ_REQ_IS_COMPUTE REG_BIT(28)
sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
229
#define SLPC_OPTIMIZED_STRATEGY_COMPUTE REG_BIT(0)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
147
#define GEN12_OAM_BUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
151
#define GEN12_OAM_CONTEXT_CONTROL_TIMER_ENABLE REG_BIT(1)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
152
#define GEN12_OAM_CONTEXT_CONTROL_COUNTER_RESUME REG_BIT(0)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
156
#define GEN12_OAM_CONTROL_COUNTER_ENABLE REG_BIT(0)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
159
#define GEN12_OAM_DEBUG_BUFFER_SIZE_SELECT REG_BIT(12)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
160
#define GEN12_OAM_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
161
#define GEN12_OAM_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
162
#define GEN12_OAM_DEBUG_DISABLE_GO_1_0_REPORTS REG_BIT(2)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
163
#define GEN12_OAM_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
166
#define GEN12_OAM_STATUS_COUNTER_OVERFLOW REG_BIT(2)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
167
#define GEN12_OAM_STATUS_BUFFER_OVERFLOW REG_BIT(1)
sys/dev/pci/drm/i915/i915_perf_oa_regs.h
168
#define GEN12_OAM_STATUS_REPORT_LOST REG_BIT(0)
sys/dev/pci/drm/i915/i915_reg.h
1022
#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
sys/dev/pci/drm/i915/i915_reg.h
1023
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
sys/dev/pci/drm/i915/i915_reg.h
1028
#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
1029
#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
sys/dev/pci/drm/i915/i915_reg.h
1032
#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
sys/dev/pci/drm/i915/i915_reg.h
1033
#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
sys/dev/pci/drm/i915/i915_reg.h
1038
#define INVERT_DDIE_HPD REG_BIT(28)
sys/dev/pci/drm/i915/i915_reg.h
1039
#define INVERT_DDID_HPD_MTP REG_BIT(27)
sys/dev/pci/drm/i915/i915_reg.h
1040
#define INVERT_TC4_HPD REG_BIT(26)
sys/dev/pci/drm/i915/i915_reg.h
1041
#define INVERT_TC3_HPD REG_BIT(25)
sys/dev/pci/drm/i915/i915_reg.h
1042
#define INVERT_TC2_HPD REG_BIT(24)
sys/dev/pci/drm/i915/i915_reg.h
1043
#define INVERT_TC1_HPD REG_BIT(23)
sys/dev/pci/drm/i915/i915_reg.h
1054
#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
sys/dev/pci/drm/i915/i915_reg.h
1120
#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
sys/dev/pci/drm/i915/i915_reg.h
1121
#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
1150
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
sys/dev/pci/drm/i915/i915_reg.h
1152
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
sys/dev/pci/drm/i915/i915_reg.h
1166
#define POWER_SETUP_I1_WATTS REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
120
#define DEPRESENT REG_BIT(9)
sys/dev/pci/drm/i915/i915_reg.h
1223
#define SGSI_SIDECLK_DIS REG_BIT(17)
sys/dev/pci/drm/i915/i915_reg.h
1224
#define SGGI_DIS REG_BIT(15)
sys/dev/pci/drm/i915/i915_reg.h
1225
#define SGR_DIS REG_BIT(13)
sys/dev/pci/drm/i915/i915_reg.h
123
#define LMEM_INIT REG_BIT(7)
sys/dev/pci/drm/i915/i915_reg.h
124
#define DRIVERFLR REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
126
#define DRIVERFLR_STATUS REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
282
#define HECI_H_CSR_IE REG_BIT(0)
sys/dev/pci/drm/i915/i915_reg.h
283
#define HECI_H_CSR_IS REG_BIT(1)
sys/dev/pci/drm/i915/i915_reg.h
284
#define HECI_H_CSR_IG REG_BIT(2)
sys/dev/pci/drm/i915/i915_reg.h
285
#define HECI_H_CSR_RDY REG_BIT(3)
sys/dev/pci/drm/i915/i915_reg.h
286
#define HECI_H_CSR_RST REG_BIT(4)
sys/dev/pci/drm/i915/i915_reg.h
289
#define HECI_H_GS1_ER_PREP REG_BIT(0)
sys/dev/pci/drm/i915/i915_reg.h
299
#define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
sys/dev/pci/drm/i915/i915_reg.h
355
#define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
358
#define CLAIM_ER_CLR REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
359
#define CLAIM_ER_OVERFLOW REG_BIT(16)
sys/dev/pci/drm/i915/i915_reg.h
415
#define FW_BLC_SELF_EN_MASK REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
416
#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
sys/dev/pci/drm/i915/i915_reg.h
417
#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
sys/dev/pci/drm/i915/i915_reg.h
508
#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
sys/dev/pci/drm/i915/i915_reg.h
512
#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
sys/dev/pci/drm/i915/i915_reg.h
584
#define ILK_FBCQ_DIS REG_BIT(22)
sys/dev/pci/drm/i915/i915_reg.h
585
#define ILK_PABSTRETCH_DIS REG_BIT(21)
sys/dev/pci/drm/i915/i915_reg.h
586
#define ILK_SABSTRETCH_DIS REG_BIT(20)
sys/dev/pci/drm/i915/i915_reg.h
746
#define PROCHOT_MASK REG_BIT(0)
sys/dev/pci/drm/i915/i915_reg.h
747
#define THERMAL_LIMIT_MASK REG_BIT(1)
sys/dev/pci/drm/i915/i915_reg.h
748
#define RATL_MASK REG_BIT(5)
sys/dev/pci/drm/i915/i915_reg.h
749
#define VR_THERMALERT_MASK REG_BIT(6)
sys/dev/pci/drm/i915/i915_reg.h
750
#define VR_TDC_MASK REG_BIT(7)
sys/dev/pci/drm/i915/i915_reg.h
751
#define POWER_LIMIT_4_MASK REG_BIT(8)
sys/dev/pci/drm/i915/i915_reg.h
752
#define POWER_LIMIT_1_MASK REG_BIT(10)
sys/dev/pci/drm/i915/i915_reg.h
753
#define POWER_LIMIT_2_MASK REG_BIT(11)
sys/dev/pci/drm/i915/i915_reg.h
765
#define DARBF_GATING_DIS REG_BIT(27)
sys/dev/pci/drm/i915/i915_reg.h
766
#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
sys/dev/pci/drm/i915/i915_reg.h
767
#define PWM2_GATING_DIS REG_BIT(14)
sys/dev/pci/drm/i915/i915_reg.h
768
#define PWM1_GATING_DIS REG_BIT(13)
sys/dev/pci/drm/i915/i915_reg.h
771
#define TGL_VRH_GATING_DIS REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
772
#define DPT_GATING_DIS REG_BIT(22)
sys/dev/pci/drm/i915/i915_reg.h
775
#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
sys/dev/pci/drm/i915/i915_reg.h
776
#define PIPEB_HLINE_INT_EN REG_BIT(28)
sys/dev/pci/drm/i915/i915_reg.h
777
#define PIPEB_VBLANK_INT_EN REG_BIT(27)
sys/dev/pci/drm/i915/i915_reg.h
778
#define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
sys/dev/pci/drm/i915/i915_reg.h
779
#define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
sys/dev/pci/drm/i915/i915_reg.h
780
#define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
sys/dev/pci/drm/i915/i915_reg.h
781
#define PIPE_PSR_INT_EN REG_BIT(22)
sys/dev/pci/drm/i915/i915_reg.h
782
#define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
sys/dev/pci/drm/i915/i915_reg.h
783
#define PIPEA_HLINE_INT_EN REG_BIT(20)
sys/dev/pci/drm/i915/i915_reg.h
784
#define PIPEA_VBLANK_INT_EN REG_BIT(19)
sys/dev/pci/drm/i915/i915_reg.h
785
#define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
sys/dev/pci/drm/i915/i915_reg.h
786
#define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
sys/dev/pci/drm/i915/i915_reg.h
787
#define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
sys/dev/pci/drm/i915/i915_reg.h
788
#define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
sys/dev/pci/drm/i915/i915_reg.h
789
#define PIPEC_HLINE_INT_EN REG_BIT(12)
sys/dev/pci/drm/i915/i915_reg.h
790
#define PIPEC_VBLANK_INT_EN REG_BIT(11)
sys/dev/pci/drm/i915/i915_reg.h
791
#define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
sys/dev/pci/drm/i915/i915_reg.h
792
#define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
sys/dev/pci/drm/i915/i915_reg.h
793
#define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
sys/dev/pci/drm/i915/i915_reg.h
924
#define DG1_MSTR_IRQ REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
925
#define DG1_MSTR_TILE(t) REG_BIT(t)
sys/dev/pci/drm/i915/i915_reg.h
929
#define ILK_ELPIN_409_SELECT REG_BIT(25)
sys/dev/pci/drm/i915/i915_reg.h
930
#define ILK_DPARB_GATE REG_BIT(22)
sys/dev/pci/drm/i915/i915_reg.h
931
#define ILK_VSDPFD_FULL REG_BIT(21)
sys/dev/pci/drm/i915/i915_reg.h
934
#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
sys/dev/pci/drm/i915/i915_reg.h
935
#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
sys/dev/pci/drm/i915/i915_reg.h
936
#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8)
sys/dev/pci/drm/i915/i915_reg.h
937
#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7)
sys/dev/pci/drm/i915/i915_reg.h
938
#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5)
sys/dev/pci/drm/i915/i915_reg.h
941
#define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
sys/dev/pci/drm/i915/i915_reg.h
942
#define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
sys/dev/pci/drm/i915/i915_reg.h
945
#define IGNORE_KVMR_PIPE_A REG_BIT(23)
sys/dev/pci/drm/i915/i915_reg.h
946
#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
sys/dev/pci/drm/i915/i915_reg.h
947
#define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
sys/dev/pci/drm/i915/i915_reg.h
948
#define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
sys/dev/pci/drm/i915/i915_reg.h
949
#define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
sys/dev/pci/drm/i915/i915_reg.h
950
#define FORCE_ARB_IDLE_PLANES REG_BIT(14)
sys/dev/pci/drm/i915/i915_reg.h
951
#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
sys/dev/pci/drm/i915/i915_reg.h
952
#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
sys/dev/pci/drm/i915/i915_reg.h
955
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
sys/dev/pci/drm/i915/i915_reg.h
970
#define HSW_FBCQ_DIS REG_BIT(22)
sys/dev/pci/drm/i915/i915_reg.h
971
#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
sys/dev/pci/drm/i915/i915_reg.h
972
#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
sys/dev/pci/drm/i915/i915_reg.h
978
#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
sys/dev/pci/drm/i915/i915_reg.h
981
#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
982
#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
sys/dev/pci/drm/i915/i915_reg.h
983
#define DISP_FBC_WM_DIS REG_BIT(15)
sys/dev/pci/drm/i915/i915_reg.h
986
#define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
sys/dev/pci/drm/i915/i915_reg.h
987
#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
sys/dev/pci/drm/i915/i915_reg.h
988
#define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
sys/dev/pci/drm/i915/i915_reg.h
989
#define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
sys/dev/pci/drm/i915/i915_reg.h
990
#define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
sys/dev/pci/drm/i915/i915_reg.h
996
#define ICL_DELAY_PMRSP REG_BIT(22)
sys/dev/pci/drm/i915/i915_reg.h
997
#define DISABLE_FLR_SRC REG_BIT(15)
sys/dev/pci/drm/i915/i915_reg.h
998
#define MASK_WAKEMEM REG_BIT(13)
sys/dev/pci/drm/i915/i915_reg.h
999
#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
sys/dev/pci/drm/i915/intel_mchbar_regs.h
190
#define DG1_QCLK_REFERENCE REG_BIT(10)
sys/dev/pci/drm/i915/intel_mchbar_regs.h
224
#define PKG_PWR_LIM_1_EN REG_BIT(15)
sys/dev/pci/drm/i915/intel_mchbar_regs.h
245
#define DG1_GEAR_TYPE REG_BIT(16)
sys/dev/pci/drm/i915/pxp/intel_pxp_regs.h
19
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
