sys/arch/luna88k/stand/boot/sio.c

104

sioreg(REG(unit, WR0), WR0_ERRRST); /* Channel-A Error Reset */

sys/arch/luna88k/stand/boot/sio.c

188

while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0);

sys/arch/luna88k/stand/boot/sio.c

193

while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0);

sys/arch/luna88k/stand/boot/sio.c

204

sioreg(REG(0, WR0), WR0_CHANRST); /* Channel-A Reset */

sys/arch/luna88k/stand/boot/sio.c

209

sioreg(REG(0, WR0), WR0_RSTINT); /* Reset E/S Interrupt */

sys/arch/luna88k/stand/boot/sio.c

210

sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); /* Tx/Rx */

sys/arch/luna88k/stand/boot/sio.c

211

sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL); /* Rx */

sys/arch/luna88k/stand/boot/sio.c

212

sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS); /* Tx */

sys/arch/luna88k/stand/boot/sio.c

213

sioreg(REG(0, WR0), WR0_RSTINT); /* Reset E/S Interrupt */

sys/arch/luna88k/stand/boot/sio.c

214

sioreg(REG(0, WR1), WR1_RXALLS); /* Interrupted All Char. */

sys/arch/luna88k/stand/boot/sio.c

216

sioreg(REG(1, WR0), WR0_CHANRST); /* Channel-A Reset */

sys/arch/luna88k/stand/boot/sio.c

218

sioreg(REG(1, WR0), WR0_RSTINT); /* Reset E/S Interrupt */

sys/arch/luna88k/stand/boot/sio.c

219

sioreg(REG(1, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); /* Tx/Rx */

sys/arch/luna88k/stand/boot/sio.c

220

sioreg(REG(1, WR3), WR3_RX8BIT | WR3_RXENBL); /* Rx */

sys/arch/luna88k/stand/boot/sio.c

221

sioreg(REG(1, WR5), WR5_TX8BIT | WR5_TXENBL); /* Tx */

sys/arch/luna88k/stand/boot/sio.c

222

sioreg(REG(1, WR0), WR0_RSTINT); /* Reset E/S Interrupt */

sys/arch/luna88k/stand/boot/sio.c

223

sioreg(REG(1, WR1), WR1_RXALLS); /* Interrupted All Char. */

sys/arch/luna88k/stand/boot/sio.c

96

int rr0 = sioreg(REG(unit, RR0), 0);

sys/arch/luna88k/stand/boot/sio.c

97

int rr1 = sioreg(REG(unit, RR1), 0);

sys/arch/sh/sh/devreg.c

101

SH ## x ## REG(TRA); \

sys/arch/sh/sh/devreg.c

102

SH ## x ## REG(EXPEVT); \

sys/arch/sh/sh/devreg.c

103

SH ## x ## REG(INTEVT); \

sys/arch/sh/sh/devreg.c

105

SH ## x ## REG(BARA); \

sys/arch/sh/sh/devreg.c

106

SH ## x ## REG(BAMRA); \

sys/arch/sh/sh/devreg.c

107

SH ## x ## REG(BASRA); \

sys/arch/sh/sh/devreg.c

108

SH ## x ## REG(BBRA); \

sys/arch/sh/sh/devreg.c

109

SH ## x ## REG(BARB); \

sys/arch/sh/sh/devreg.c

110

SH ## x ## REG(BAMRB); \

sys/arch/sh/sh/devreg.c

111

SH ## x ## REG(BASRB); \

sys/arch/sh/sh/devreg.c

112

SH ## x ## REG(BBRB); \

sys/arch/sh/sh/devreg.c

113

SH ## x ## REG(BDRB); \

sys/arch/sh/sh/devreg.c

114

SH ## x ## REG(BDMRB); \

sys/arch/sh/sh/devreg.c

115

SH ## x ## REG(BRCR); \

sys/arch/sh/sh/devreg.c

117

SH ## x ## REG(PTEH); \

sys/arch/sh/sh/devreg.c

118

SH ## x ## REG(TEA); \

sys/arch/sh/sh/devreg.c

119

SH ## x ## REG(TTB); \

sys/arch/sh/sh/devreg.c

121

SH ## x ## REG(R64CNT); \

sys/arch/sh/sh/devreg.c

122

SH ## x ## REG(RSECCNT); \

sys/arch/sh/sh/devreg.c

123

SH ## x ## REG(RMINCNT); \

sys/arch/sh/sh/devreg.c

124

SH ## x ## REG(RHRCNT); \

sys/arch/sh/sh/devreg.c

125

SH ## x ## REG(RWKCNT); \

sys/arch/sh/sh/devreg.c

126

SH ## x ## REG(RDAYCNT); \

sys/arch/sh/sh/devreg.c

127

SH ## x ## REG(RMONCNT); \

sys/arch/sh/sh/devreg.c

128

SH ## x ## REG(RYRCNT); \

sys/arch/sh/sh/devreg.c

129

SH ## x ## REG(RSECAR); \

sys/arch/sh/sh/devreg.c

130

SH ## x ## REG(RMINAR); \

sys/arch/sh/sh/devreg.c

131

SH ## x ## REG(RHRAR); \

sys/arch/sh/sh/devreg.c

132

SH ## x ## REG(RWKAR); \

sys/arch/sh/sh/devreg.c

133

SH ## x ## REG(RDAYAR); \

sys/arch/sh/sh/devreg.c

134

SH ## x ## REG(RMONAR); \

sys/arch/sh/sh/devreg.c

135

SH ## x ## REG(RCR1); \

sys/arch/sh/sh/devreg.c

136

SH ## x ## REG(RCR2); \

sys/arch/sh/sh/devreg.c

138

SH ## x ## REG(TOCR); \

sys/arch/sh/sh/devreg.c

139

SH ## x ## REG(TSTR); \

sys/arch/sh/sh/devreg.c

140

SH ## x ## REG(TCOR0); \

sys/arch/sh/sh/devreg.c

141

SH ## x ## REG(TCNT0); \

sys/arch/sh/sh/devreg.c

142

SH ## x ## REG(TCR0); \

sys/arch/sh/sh/devreg.c

143

SH ## x ## REG(TCOR1); \

sys/arch/sh/sh/devreg.c

144

SH ## x ## REG(TCNT1); \

sys/arch/sh/sh/devreg.c

145

SH ## x ## REG(TCR1); \

sys/arch/sh/sh/devreg.c

146

SH ## x ## REG(TCOR2); \

sys/arch/sh/sh/devreg.c

147

SH ## x ## REG(TCNT2); \

sys/arch/sh/sh/devreg.c

148

SH ## x ## REG(TCR2); \

sys/arch/sh/sh/devreg.c

149

SH ## x ## REG(TCPR2); \

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

384

if (REG(DSCCLK3_DTO_PARAM)) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

428

if (REG(DSCCLK3_DTO_PARAM)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

132

if (REG(AUX_RESET_MASK)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

143

if (REG(AUX_RESET_MASK)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

197

if (REG(AUXN_IMPCAL)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

1001

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

250

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

262

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

267

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

315

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

689

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

701

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

706

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

741

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

963

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

966

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

969

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

177

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

209

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

305

ASSERT(REG(DP_DPHY_INTERNAL_CTRL));

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

446

if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

498

if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

236

if (REG(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

249

if (REG(DPG_PIPE_LOW_POWER_CONTROL)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

286

if (REG(DPG_PIPE_STUTTER_CONTROL2))

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

304

if (REG(DPG_PIPE_STUTTER_CONTROL2))

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

332

if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

130

if (!REG(AFMT_VBI_PACKET_CONTROL1)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

137

if (REG(AFMT_VBI_PACKET_CONTROL1)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1381

if (REG(AFMT_CNTL) == 0)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

230

if (REG(HDMI_GENERIC_PACKET_CONTROL2))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

237

if (REG(HDMI_GENERIC_PACKET_CONTROL2))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

244

if (REG(HDMI_GENERIC_PACKET_CONTROL3))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

251

if (REG(HDMI_GENERIC_PACKET_CONTROL3))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

332

if (REG(DP_MSA_MISC))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

384

if (REG(DP_MSA_TIMING_PARAM1)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

443

if (REG(DP_MSA_COLORIMETRY))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

446

if (REG(DP_MSA_MISC))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

452

if (REG(DP_MSA_TIMING_PARAM1))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

477

if (REG(DP_MSA_TIMING_PARAM2))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

482

if (REG(DP_MSA_TIMING_PARAM3))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

494

if (REG(DP_MSA_TIMING_PARAM4))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

73

if (REG(AFMT_CNTL))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

737

if (REG(AFMT_CNTL))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

76

if (REG(AFMT_VBI_PACKET_CONTROL1)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

775

if (REG(HDMI_DB_CONTROL))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

810

if (REG(HDMI_GENERIC_PACKET_CONTROL2))

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

819

if (REG(HDMI_GENERIC_PACKET_CONTROL3))

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1423

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1431

if (REG(DCFE_MEM_PWR_STATUS)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1477

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1581

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

227

if (REG(DCFE_MEM_PWR_CTRL)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

261

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

233

if (!REG(DP_DPHY_INTERNAL_CTRL))

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

378

if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1371

if (REG(AFMT_CNTL) == 0)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

125

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

126

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

135

gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

136

gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

145

gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

146

gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

203

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

204

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

213

gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

214

gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

223

gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

224

gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

288

gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

289

gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

293

gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

294

gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

442

gam_regs.start_cntl_b = REG(CM_RGAM_RAMA_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

443

gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

444

gam_regs.start_cntl_r = REG(CM_RGAM_RAMA_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

445

gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMA_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

446

gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMA_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

447

gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMA_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

448

gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMA_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

449

gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMA_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

450

gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMA_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

451

gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMA_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

452

gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMA_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

453

gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMA_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

454

gam_regs.region_start = REG(CM_RGAM_RAMA_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

455

gam_regs.region_end = REG(CM_RGAM_RAMA_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

471

gam_regs.start_cntl_b = REG(CM_RGAM_RAMB_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

472

gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

473

gam_regs.start_cntl_r = REG(CM_RGAM_RAMB_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

474

gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMB_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

475

gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMB_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

476

gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMB_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

477

gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMB_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

478

gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMB_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

479

gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMB_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

480

gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMB_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

481

gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMB_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

482

gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMB_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

483

gam_regs.region_start = REG(CM_RGAM_RAMB_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

484

gam_regs.region_end = REG(CM_RGAM_RAMB_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

545

gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

546

gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

550

gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

551

gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

595

gam_regs.start_cntl_b = REG(CM_DGAM_RAMB_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

596

gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

597

gam_regs.start_cntl_r = REG(CM_DGAM_RAMB_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

598

gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMB_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

599

gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMB_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

600

gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMB_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

601

gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMB_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

602

gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMB_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

603

gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMB_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

604

gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMB_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

605

gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMB_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

606

gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMB_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

607

gam_regs.region_start = REG(CM_DGAM_RAMB_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

608

gam_regs.region_end = REG(CM_DGAM_RAMB_REGION_14_15);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

624

gam_regs.start_cntl_b = REG(CM_DGAM_RAMA_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

625

gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

626

gam_regs.start_cntl_r = REG(CM_DGAM_RAMA_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

627

gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMA_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

628

gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMA_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

629

gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMA_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

630

gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMA_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

631

gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMA_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

632

gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMA_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

633

gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMA_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

634

gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMA_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

635

gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMA_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

636

gam_regs.region_start = REG(CM_DGAM_RAMA_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

637

gam_regs.region_end = REG(CM_DGAM_RAMA_REGION_14_15);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

549

if (REG(SCL_VERT_FILTER_INIT_BOT)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

565

if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

672

if (REG(SCL_BLACK_OFFSET)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

195

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

196

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

198

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

199

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

256

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

257

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

264

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

265

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

346

icsc_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

347

icsc_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

351

icsc_regs.csc_c11_c12 = REG(CM_ICSC_B_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

352

icsc_regs.csc_c33_c34 = REG(CM_ICSC_B_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

450

gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

451

gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

452

gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

453

gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

454

gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

455

gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

456

gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

457

gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

458

gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

459

gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

460

gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

461

gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

462

gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

463

gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

478

gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

479

gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

480

gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

481

gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

482

gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

483

gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

484

gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

485

gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

486

gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

487

gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

488

gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

489

gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

490

gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

491

gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

141

gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

142

gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

146

gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

147

gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

67

if (REG(CM_SHAPER_CONTROL))

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

69

if (REG(CM_3DLUT_MODE))

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

704

gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

705

gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

706

gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

707

gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

708

gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

709

gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

71

if (REG(CM_3DLUT_READ_WRITE_CONTROL))

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

710

gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

711

gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

712

gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

713

gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

714

gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

715

gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

716

gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

717

gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

73

if (REG(CM_3DLUT_MODE))

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

732

gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

733

gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

734

gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

735

gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

736

gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

737

gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

738

gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

739

gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

740

gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

741

gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

742

gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

743

gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

744

gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

745

gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

77

if (REG(CM_BLNDGAM_CONTROL)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

244

gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

245

gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

246

gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

247

gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

248

gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

249

gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

250

gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

251

gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

252

gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

253

gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMB_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

254

gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMB_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

255

gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMB_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

256

gam_regs.region_start = REG(CM_GAMCOR_RAMB_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

257

gam_regs.region_end = REG(CM_GAMCOR_RAMB_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

259

gam_regs.offset_b = REG(CM_GAMCOR_RAMB_OFFSET_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

260

gam_regs.offset_g = REG(CM_GAMCOR_RAMB_OFFSET_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

261

gam_regs.offset_r = REG(CM_GAMCOR_RAMB_OFFSET_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

262

gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

263

gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

264

gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

266

gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMA_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

267

gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMA_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

268

gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMA_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

269

gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

270

gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

271

gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

272

gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMA_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

273

gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMA_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

274

gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMA_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

275

gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMA_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

276

gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMA_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

277

gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMA_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

278

gam_regs.region_start = REG(CM_GAMCOR_RAMA_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

279

gam_regs.region_end = REG(CM_GAMCOR_RAMA_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

281

gam_regs.offset_b = REG(CM_GAMCOR_RAMA_OFFSET_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

282

gam_regs.offset_g = REG(CM_GAMCOR_RAMA_OFFSET_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

283

gam_regs.offset_r = REG(CM_GAMCOR_RAMA_OFFSET_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

284

gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

285

gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

286

gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

348

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

349

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

358

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

359

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

427

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

428

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

435

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

436

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

205

cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_A);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

206

cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_A);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

208

cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

209

cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_B);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1150

if (REG(SCL_BLACK_OFFSET)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

546

if (REG(SCL_VERT_FILTER_INIT_BOT)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

556

if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

596

if (REG(SCL_VERT_FILTER_INIT_BOT)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

612

if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

100

gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMA_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

101

gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMA_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

102

gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMA_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

103

gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMA_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

104

gam_regs.offset_b = REG(DWB_OGAM_RAMA_OFFSET_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

105

gam_regs.offset_g = REG(DWB_OGAM_RAMA_OFFSET_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

106

gam_regs.offset_r = REG(DWB_OGAM_RAMA_OFFSET_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

107

gam_regs.region_start = REG(DWB_OGAM_RAMA_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

108

gam_regs.region_end = REG(DWB_OGAM_RAMA_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

122

gam_regs.start_cntl_b = REG(DWB_OGAM_RAMB_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

123

gam_regs.start_cntl_g = REG(DWB_OGAM_RAMB_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

124

gam_regs.start_cntl_r = REG(DWB_OGAM_RAMB_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

125

gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMB_START_BASE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

126

gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMB_START_BASE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

127

gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMB_START_BASE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

128

gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

129

gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

130

gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

131

gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMB_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

132

gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMB_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

133

gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMB_END_CNTL1_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

134

gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMB_END_CNTL2_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

135

gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMB_END_CNTL1_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

136

gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMB_END_CNTL2_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

137

gam_regs.offset_b = REG(DWB_OGAM_RAMB_OFFSET_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

138

gam_regs.offset_g = REG(DWB_OGAM_RAMB_OFFSET_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

139

gam_regs.offset_r = REG(DWB_OGAM_RAMB_OFFSET_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

140

gam_regs.region_start = REG(DWB_OGAM_RAMB_REGION_0_1);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

141

gam_regs.region_end = REG(DWB_OGAM_RAMB_REGION_32_33);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

325

gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPA_C11_C12);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

326

gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPA_C33_C34);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

334

gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPB_C11_C12);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

335

gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPB_C33_C34);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

89

gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

90

gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

91

gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

92

gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

93

gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

94

gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

95

gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

96

gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

97

gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_R);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

98

gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMA_END_CNTL1_B);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

99

gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMA_END_CNTL2_B);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

126

case REG(DC_GPIO_SYNCA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

141

case REG(DC_GPIO_GENLK_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

165

case REG(DC_GPIO_DDC1_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

168

case REG(DC_GPIO_DDC2_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

171

case REG(DC_GPIO_DDC3_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

174

case REG(DC_GPIO_DDC4_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

177

case REG(DC_GPIO_DDC5_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

180

case REG(DC_GPIO_DDC6_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

183

case REG(DC_GPIO_DDCVGA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

187

case REG(DC_GPIO_I2CPAD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

191

case REG(DC_GPIO_PWRSEQ_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

192

case REG(DC_GPIO_PAD_STRENGTH_1):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

193

case REG(DC_GPIO_PAD_STRENGTH_2):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

194

case REG(DC_GPIO_DEBUG):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

215

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

218

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

221

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

224

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

227

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

230

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

233

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

236

info->offset = REG(DC_GPIO_I2CPAD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

247

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

250

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

253

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

256

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

259

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

262

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

265

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

268

info->offset = REG(DC_GPIO_I2CPAD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

276

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

305

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

333

info->offset = REG(DC_GPIO_SYNCA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

337

info->offset = REG(DC_GPIO_SYNCA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

350

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

354

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

359

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

363

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

69

case REG(DC_GPIO_GENERIC_A):

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

99

case REG(DC_GPIO_HPD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

126

case REG(DC_GPIO_SYNCA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

141

case REG(DC_GPIO_GENLK_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

165

case REG(DC_GPIO_DDC1_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

168

case REG(DC_GPIO_DDC2_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

171

case REG(DC_GPIO_DDC3_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

174

case REG(DC_GPIO_DDC4_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

177

case REG(DC_GPIO_DDC5_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

180

case REG(DC_GPIO_DDC6_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

183

case REG(DC_GPIO_DDCVGA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

187

case REG(DC_GPIO_I2CPAD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

191

case REG(DC_GPIO_PWRSEQ_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

192

case REG(DC_GPIO_PAD_STRENGTH_1):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

193

case REG(DC_GPIO_PAD_STRENGTH_2):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

194

case REG(DC_GPIO_DEBUG):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

215

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

218

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

221

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

224

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

227

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

230

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

233

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

236

info->offset = REG(DC_GPIO_I2CPAD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

247

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

250

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

253

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

256

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

259

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

262

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

265

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

268

info->offset = REG(DC_GPIO_I2CPAD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

276

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

305

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

333

info->offset = REG(DC_GPIO_SYNCA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

337

info->offset = REG(DC_GPIO_SYNCA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

350

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

354

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

359

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

363

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

69

case REG(DC_GPIO_GENERIC_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

99

case REG(DC_GPIO_HPD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

103

case REG(DC_GPIO_HPD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

130

case REG(DC_GPIO_GENLK_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

155

case REG(DC_GPIO_DDC1_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

158

case REG(DC_GPIO_DDC2_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

161

case REG(DC_GPIO_DDC3_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

164

case REG(DC_GPIO_DDC4_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

167

case REG(DC_GPIO_DDC5_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

170

case REG(DC_GPIO_DDC6_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

173

case REG(DC_GPIO_DDCVGA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

204

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

207

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

210

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

213

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

216

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

219

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

222

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

234

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

237

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

240

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

243

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

246

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

249

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

252

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

261

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

290

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

73

case REG(DC_GPIO_GENERIC_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

102

case REG(DC_GPIO_HPD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

129

case REG(DC_GPIO_GENLK_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

154

case REG(DC_GPIO_DDC1_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

157

case REG(DC_GPIO_DDC2_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

160

case REG(DC_GPIO_DDC3_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

163

case REG(DC_GPIO_DDC4_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

166

case REG(DC_GPIO_DDC5_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

169

case REG(DC_GPIO_DDCVGA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

200

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

203

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

206

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

209

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

212

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

215

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

227

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

230

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

233

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

236

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

239

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

242

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

251

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

280

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

72

case REG(DC_GPIO_GENERIC_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

110

case REG(DC_GPIO_HPD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

137

case REG(DC_GPIO_GENLK_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

162

case REG(DC_GPIO_DDC1_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

165

case REG(DC_GPIO_DDC2_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

168

case REG(DC_GPIO_DDC3_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

171

case REG(DC_GPIO_DDC4_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

174

case REG(DC_GPIO_DDC5_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

177

case REG(DC_GPIO_DDC6_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

180

case REG(DC_GPIO_DDCVGA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

211

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

214

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

217

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

220

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

223

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

226

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

229

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

241

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

244

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

247

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

250

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

253

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

256

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

259

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

268

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

297

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

80

case REG(DC_GPIO_GENERIC_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

103

case REG(DC_GPIO_HPD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

130

case REG(DC_GPIO_GENLK_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

155

case REG(DC_GPIO_DDC1_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

158

case REG(DC_GPIO_DDC2_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

161

case REG(DC_GPIO_DDC3_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

164

case REG(DC_GPIO_DDC4_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

167

case REG(DC_GPIO_DDC5_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

170

case REG(DC_GPIO_DDCVGA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

201

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

204

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

207

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

210

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

213

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

216

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

228

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

231

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

234

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

237

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

240

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

243

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

252

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

281

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

73

case REG(DC_GPIO_GENERIC_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

122

case REG(DC_GPIO_GENLK_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

146

case REG(DC_GPIO_DDC1_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

149

case REG(DC_GPIO_DDC2_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

152

case REG(DC_GPIO_DDC3_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

155

case REG(DC_GPIO_DDC4_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

158

case REG(DC_GPIO_DDC5_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

161

case REG(DC_GPIO_DDCVGA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

182

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

185

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

188

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

191

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

194

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

197

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

209

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

212

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

215

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

218

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

221

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

224

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

233

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

259

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

71

case REG(DC_GPIO_GENERIC_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

98

case REG(DC_GPIO_HPD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

122

case REG(DC_GPIO_DDC1_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

125

case REG(DC_GPIO_DDC2_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

128

case REG(DC_GPIO_DDC3_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

131

case REG(DC_GPIO_DDC4_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

134

case REG(DC_GPIO_DDCVGA_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

166

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

169

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

172

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

175

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

181

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

193

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

196

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

199

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

202

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

208

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

217

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

243

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

46

case REG(DC_GPIO_GENERIC_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

73

case REG(DC_GPIO_HPD_A):

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

97

case REG(DC_GPIO_GENLK_A):

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

35

.type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

49

.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

53

.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

54

.phy_aux_cntl = REG(PHY_AUX_CNTL), \

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

55

.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

58

.type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

75

.type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

94

.phy_aux_cntl = REG(PHY_AUX_CNTL), \

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

95

.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)

sys/dev/pci/drm/amd/display/dc/gpio/generic_regs.h

32

.type ## _reg = REG(DC_GPIO_GENERIC_## type),\

sys/dev/pci/drm/amd/display/dc/gpio/generic_regs.h

46

.mux = REG(DC_GENERIC ## id),\

sys/dev/pci/drm/amd/display/dc/gpio/hpd_regs.h

40

.type ## _reg = REG(DC_GPIO_HPD_## type),\

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

54

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

625

if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

64

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

74

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

84

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

436

if (REG(DCN_VM_FB_LOCATION_TOP) == 0)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

518

if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A))

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

520

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

529

if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B))

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

531

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

540

if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C))

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

542

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

551

if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D))

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

553

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

634

if (REG(DCN_VM_FAULT_ADDR_MSB))

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

637

if (REG(DCN_VM_FAULT_ADDR_LSB))

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

640

if (REG(DCN_VM_FAULT_CNTL))

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

643

if (REG(DCN_VM_FAULT_STATUS)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

649

if (REG(DCHUBBUB_TEST_DEBUG_INDEX) && REG(DCHUBBUB_TEST_DEBUG_DATA)) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

654

if (REG(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL))

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

657

if (REG(DCHUBBUB_ARB_DRAM_STATE_CNTL))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1000

if (REG(NOM_PARAMETERS_3))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

635

if (REG(NOM_PARAMETERS_0))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

639

if (REG(NOM_PARAMETERS_1))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

656

if (REG(NOM_PARAMETERS_2))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

660

if (REG(NOM_PARAMETERS_3))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

938

if (REG(PREFETCH_SETTINS))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

961

if (REG(NOM_PARAMETERS_0))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

965

if (REG(NOM_PARAMETERS_1))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

983

if (REG(PREFETCH_SETTINS_C))

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

996

if (REG(NOM_PARAMETERS_2))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

110

if (REG(NOM_PARAMETERS_0))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

114

if (REG(NOM_PARAMETERS_1))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1169

if (REG(PREFETCH_SETTINS))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1192

if (REG(NOM_PARAMETERS_0))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1196

if (REG(NOM_PARAMETERS_1))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1214

if (REG(PREFETCH_SETTINS_C))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1227

if (REG(NOM_PARAMETERS_2))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1231

if (REG(NOM_PARAMETERS_3))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

131

if (REG(NOM_PARAMETERS_2))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

135

if (REG(NOM_PARAMETERS_3))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1351

if (REG(DCHUBP_CNTL))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1354

if (REG(DCSURF_FLIP_CONTROL))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1504

if (REG(NOM_PARAMETERS_0))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1507

if (REG(NOM_PARAMETERS_1))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1522

if (REG(NOM_PARAMETERS_2))

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1525

if (REG(NOM_PARAMETERS_3))

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

395

if (REG(NOM_PARAMETERS_0))

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

398

if (REG(NOM_PARAMETERS_1))

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

413

if (REG(NOM_PARAMETERS_2))

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

416

if (REG(NOM_PARAMETERS_3))

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

468

if (REG(UCLK_PSTATE_FORCE))

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

471

if (REG(DCHUBP_CNTL))

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

474

if (REG(DCSURF_FLIP_CONTROL))

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

280

if (REG(NOM_PARAMETERS_0))

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

284

if (REG(NOM_PARAMETERS_1))

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

301

if (REG(NOM_PARAMETERS_2))

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

305

if (REG(NOM_PARAMETERS_3))

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

120

if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

140

if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

148

if (REG(DCFEV_CLOCK_CONTROL))

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

200

if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1016

if (REG(DC_IP_REQUEST_CNTL)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1494

if (REG(DC_IP_REQUEST_CNTL)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

257

if (REG(MPC_CRC_RESULT_GB))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

260

if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

904

if (REG(DOMAIN1_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

965

if (REG(DOMAIN0_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1291

if (REG(DC_IP_REQUEST_CNTL)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3157

if (REG(REFCLK_CNTL))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

326

if (REG(DOMAIN8_PG_CONFIG))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

328

if (REG(DOMAIN10_PG_CONFIG))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

336

if (REG(DOMAIN9_PG_CONFIG))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

338

if (REG(DOMAIN11_PG_CONFIG))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

345

if (REG(DOMAIN19_PG_CONFIG))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

347

if (REG(DOMAIN20_PG_CONFIG))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

349

if (REG(DOMAIN21_PG_CONFIG))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

486

if (REG(DOMAIN16_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

561

if (REG(DOMAIN1_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

643

if (REG(DOMAIN0_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

109

if (REG(DOMAIN0_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

168

if (REG(DOMAIN16_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

52

if (REG(DOMAIN1_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

456

if (REG(DOMAIN0_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

562

if (REG(DOMAIN1_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

171

if (REG(DOMAIN0_PG_CONFIG) == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2658

if (REG(DC_IP_REQUEST_CNTL)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2674

if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL))

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

157

generic_reg_get(CTX, REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

161

generic_reg_get2(CTX, REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

166

generic_reg_get3(CTX, REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

172

generic_reg_get4(CTX, REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

179

generic_reg_get5(CTX, REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

187

generic_reg_get6(CTX, REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

196

generic_reg_get7(CTX, REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

206

generic_reg_get8(CTX, REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

220

REG(reg_name), FN(reg_name, field), val,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

227

REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

40

dm_read_reg(CTX, REG(reg_name))

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

43

dm_write_reg(CTX, REG(reg_name), value)

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

448

REG(index_reg_name), REG(data_reg_name), IND_REG(index), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

459

generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index))

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

462

generic_indirect_reg_get(CTX, REG(index_reg_name), REG(data_reg_name), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

472

REG(index_reg_name), REG(data_reg_name), IND_REG(index), \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

56

REG(reg_name), \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

372

if (REG(MUX[opp_id]))

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

391

if (opp_id < MAX_OPP && REG(MUX[opp_id]))

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

472

if (opp_id < MAX_OPP && REG(MUX[opp_id]))

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

170

ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

171

ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

173

ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

174

ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

229

ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

230

ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

232

ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

233

ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

330

gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

331

gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

332

gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

333

gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

334

gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

335

gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

336

gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

337

gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

338

gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

339

gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

340

gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

341

gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

342

gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

343

gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

357

gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

358

gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

359

gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

360

gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

361

gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

362

gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

363

gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

364

gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

365

gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

366

gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

367

gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

368

gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

369

gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

370

gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1101

gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1102

gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1111

gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1112

gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1176

gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1177

gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1186

gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1187

gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1330

ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1331

ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1333

ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1334

ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1373

ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1374

ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1376

ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1377

ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

243

gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

244

gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

245

gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

246

gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

247

gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

248

gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

249

gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

250

gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

251

gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

252

gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

253

gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

254

gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

255

gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

256

gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

258

gam_regs.offset_b = REG(MPCC_OGAM_RAMA_OFFSET_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

259

gam_regs.offset_g = REG(MPCC_OGAM_RAMA_OFFSET_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

260

gam_regs.offset_r = REG(MPCC_OGAM_RAMA_OFFSET_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

261

gam_regs.start_base_cntl_b = REG(MPCC_OGAM_RAMA_START_BASE_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

262

gam_regs.start_base_cntl_g = REG(MPCC_OGAM_RAMA_START_BASE_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

263

gam_regs.start_base_cntl_r = REG(MPCC_OGAM_RAMA_START_BASE_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

276

gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

277

gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

278

gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

279

gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

280

gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

281

gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

282

gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

283

gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

284

gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

285

gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

286

gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

287

gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

288

gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

289

gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

291

gam_regs.offset_b = REG(MPCC_OGAM_RAMB_OFFSET_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

292

gam_regs.offset_g = REG(MPCC_OGAM_RAMB_OFFSET_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

293

gam_regs.offset_r = REG(MPCC_OGAM_RAMB_OFFSET_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

294

gam_regs.start_base_cntl_b = REG(MPCC_OGAM_RAMB_START_BASE_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

295

gam_regs.start_base_cntl_g = REG(MPCC_OGAM_RAMB_START_BASE_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

296

gam_regs.start_base_cntl_r = REG(MPCC_OGAM_RAMB_START_BASE_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

55

if (REG(MUX[opp_id]))

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

71

if (mpcc_id < MAX_OPP && REG(MUX[mpcc_id]))

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

177

gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

178

gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

179

gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

180

gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

181

gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

182

gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

183

gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

184

gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

185

gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

186

gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

187

gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

188

gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

189

gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMA_REGION_0_1[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

190

gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMA_REGION_32_33[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

206

gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

207

gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

208

gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

209

gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

210

gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

211

gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

212

gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

213

gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

214

gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

215

gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

216

gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

217

gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

218

gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMB_REGION_0_1[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

219

gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMB_REGION_32_33[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

316

gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

317

gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

320

gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

321

gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

350

gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

351

gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

354

gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

355

gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

385

gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

386

gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

389

gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

390

gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

482

gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

483

gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

486

gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

487

gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

505

gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

506

gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

509

gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

510

gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

528

gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

529

gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

532

gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

533

gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

268

if (REG(OTG_INTERLACE_CONTROL)) {

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

308

if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) {

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

374

if (REG(OTG_INTERLACE_CONTROL)) {

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

204

if (REG(OPTC_MEMORY_CONFIG))

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

249

if (REG(OPTC_MEMORY_CONFIG))

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

67

if (REG(OPTC_MEMORY_CONFIG))

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

112

dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

51

#define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

54

((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

59

dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

86

dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)

sys/dev/pci/drm/i915/gt/intel_lrc.c

110

REG(0x034),

sys/dev/pci/drm/i915/gt/intel_lrc.c

111

REG(0x030),

sys/dev/pci/drm/i915/gt/intel_lrc.c

112

REG(0x038),

sys/dev/pci/drm/i915/gt/intel_lrc.c

113

REG(0x03c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

114

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

115

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

116

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

117

REG(0x11c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

118

REG(0x114),

sys/dev/pci/drm/i915/gt/intel_lrc.c

119

REG(0x118),

sys/dev/pci/drm/i915/gt/intel_lrc.c

136

REG(0x028),

sys/dev/pci/drm/i915/gt/intel_lrc.c

145

REG(0x034),

sys/dev/pci/drm/i915/gt/intel_lrc.c

146

REG(0x030),

sys/dev/pci/drm/i915/gt/intel_lrc.c

147

REG(0x038),

sys/dev/pci/drm/i915/gt/intel_lrc.c

148

REG(0x03c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

149

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

150

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

151

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

152

REG(0x11c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

153

REG(0x114),

sys/dev/pci/drm/i915/gt/intel_lrc.c

154

REG(0x118),

sys/dev/pci/drm/i915/gt/intel_lrc.c

155

REG(0x1c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

156

REG(0x1c4),

sys/dev/pci/drm/i915/gt/intel_lrc.c

157

REG(0x1c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

177

REG(0x028),

sys/dev/pci/drm/i915/gt/intel_lrc.c

178

REG(0x09c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

179

REG(0x0c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

180

REG(0x178),

sys/dev/pci/drm/i915/gt/intel_lrc.c

181

REG(0x17c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

183

REG(0x170),

sys/dev/pci/drm/i915/gt/intel_lrc.c

184

REG(0x150),

sys/dev/pci/drm/i915/gt/intel_lrc.c

185

REG(0x154),

sys/dev/pci/drm/i915/gt/intel_lrc.c

186

REG(0x158),

sys/dev/pci/drm/i915/gt/intel_lrc.c

220

REG(0x068),

sys/dev/pci/drm/i915/gt/intel_lrc.c

229

REG(0x034),

sys/dev/pci/drm/i915/gt/intel_lrc.c

230

REG(0x030),

sys/dev/pci/drm/i915/gt/intel_lrc.c

231

REG(0x038),

sys/dev/pci/drm/i915/gt/intel_lrc.c

232

REG(0x03c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

233

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

234

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

235

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

236

REG(0x1c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

237

REG(0x1c4),

sys/dev/pci/drm/i915/gt/intel_lrc.c

238

REG(0x1c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

239

REG(0x180),

sys/dev/pci/drm/i915/gt/intel_lrc.c

261

REG(0x034),

sys/dev/pci/drm/i915/gt/intel_lrc.c

262

REG(0x030),

sys/dev/pci/drm/i915/gt/intel_lrc.c

263

REG(0x038),

sys/dev/pci/drm/i915/gt/intel_lrc.c

264

REG(0x03c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

265

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

266

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

267

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

268

REG(0x1c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

269

REG(0x1c4),

sys/dev/pci/drm/i915/gt/intel_lrc.c

270

REG(0x1c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

271

REG(0x180),

sys/dev/pci/drm/i915/gt/intel_lrc.c

273

REG(0x120),

sys/dev/pci/drm/i915/gt/intel_lrc.c

274

REG(0x124),

sys/dev/pci/drm/i915/gt/intel_lrc.c

295

REG(0x034),

sys/dev/pci/drm/i915/gt/intel_lrc.c

296

REG(0x030),

sys/dev/pci/drm/i915/gt/intel_lrc.c

297

REG(0x038),

sys/dev/pci/drm/i915/gt/intel_lrc.c

298

REG(0x03c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

299

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

300

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

301

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

302

REG(0x11c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

303

REG(0x114),

sys/dev/pci/drm/i915/gt/intel_lrc.c

304

REG(0x118),

sys/dev/pci/drm/i915/gt/intel_lrc.c

305

REG(0x1c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

306

REG(0x1c4),

sys/dev/pci/drm/i915/gt/intel_lrc.c

307

REG(0x1c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

323

REG(0x0c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

332

REG(0x34),

sys/dev/pci/drm/i915/gt/intel_lrc.c

333

REG(0x30),

sys/dev/pci/drm/i915/gt/intel_lrc.c

334

REG(0x38),

sys/dev/pci/drm/i915/gt/intel_lrc.c

335

REG(0x3c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

336

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

337

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

338

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

339

REG(0x11c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

340

REG(0x114),

sys/dev/pci/drm/i915/gt/intel_lrc.c

341

REG(0x118),

sys/dev/pci/drm/i915/gt/intel_lrc.c

342

REG(0x1c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

343

REG(0x1c4),

sys/dev/pci/drm/i915/gt/intel_lrc.c

344

REG(0x1c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

360

REG(0xc8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

364

REG(0x28),

sys/dev/pci/drm/i915/gt/intel_lrc.c

365

REG(0x9c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

366

REG(0xc0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

367

REG(0x178),

sys/dev/pci/drm/i915/gt/intel_lrc.c

368

REG(0x17c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

370

REG(0x170),

sys/dev/pci/drm/i915/gt/intel_lrc.c

371

REG(0x150),

sys/dev/pci/drm/i915/gt/intel_lrc.c

372

REG(0x154),

sys/dev/pci/drm/i915/gt/intel_lrc.c

373

REG(0x158),

sys/dev/pci/drm/i915/gt/intel_lrc.c

407

REG(0x68),

sys/dev/pci/drm/i915/gt/intel_lrc.c

416

REG(0x034),

sys/dev/pci/drm/i915/gt/intel_lrc.c

417

REG(0x030),

sys/dev/pci/drm/i915/gt/intel_lrc.c

418

REG(0x038),

sys/dev/pci/drm/i915/gt/intel_lrc.c

419

REG(0x03c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

420

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

421

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

422

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

423

REG(0x11c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

424

REG(0x114),

sys/dev/pci/drm/i915/gt/intel_lrc.c

425

REG(0x118),

sys/dev/pci/drm/i915/gt/intel_lrc.c

426

REG(0x1c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

427

REG(0x1c4),

sys/dev/pci/drm/i915/gt/intel_lrc.c

428

REG(0x1c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

429

REG(0x180),

sys/dev/pci/drm/i915/gt/intel_lrc.c

444

REG(0x1b0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

448

REG(0x0c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

457

REG(0x034),

sys/dev/pci/drm/i915/gt/intel_lrc.c

458

REG(0x030),

sys/dev/pci/drm/i915/gt/intel_lrc.c

459

REG(0x038),

sys/dev/pci/drm/i915/gt/intel_lrc.c

460

REG(0x03c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

461

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

462

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

463

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

464

REG(0x1c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

465

REG(0x1c4),

sys/dev/pci/drm/i915/gt/intel_lrc.c

466

REG(0x1c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

467

REG(0x180),

sys/dev/pci/drm/i915/gt/intel_lrc.c

483

REG(0x1b0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

489

REG(0x0c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

499

REG(0x028),

sys/dev/pci/drm/i915/gt/intel_lrc.c

500

REG(0x09c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

501

REG(0x0c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

502

REG(0x178),

sys/dev/pci/drm/i915/gt/intel_lrc.c

503

REG(0x17c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

505

REG(0x170),

sys/dev/pci/drm/i915/gt/intel_lrc.c

506

REG(0x150),

sys/dev/pci/drm/i915/gt/intel_lrc.c

507

REG(0x154),

sys/dev/pci/drm/i915/gt/intel_lrc.c

508

REG(0x158),

sys/dev/pci/drm/i915/gt/intel_lrc.c

542

REG(0x068),

sys/dev/pci/drm/i915/gt/intel_lrc.c

543

REG(0x084),

sys/dev/pci/drm/i915/gt/intel_lrc.c

553

REG(0x034),

sys/dev/pci/drm/i915/gt/intel_lrc.c

554

REG(0x030),

sys/dev/pci/drm/i915/gt/intel_lrc.c

555

REG(0x038),

sys/dev/pci/drm/i915/gt/intel_lrc.c

556

REG(0x03c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

557

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

558

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

559

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

560

REG(0x1c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

561

REG(0x1c4),

sys/dev/pci/drm/i915/gt/intel_lrc.c

562

REG(0x1c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

563

REG(0x180),

sys/dev/pci/drm/i915/gt/intel_lrc.c

565

REG(0x120),

sys/dev/pci/drm/i915/gt/intel_lrc.c

566

REG(0x124),

sys/dev/pci/drm/i915/gt/intel_lrc.c

581

REG(0x1b0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

587

REG(0x0c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

596

REG(0x034),

sys/dev/pci/drm/i915/gt/intel_lrc.c

597

REG(0x030),

sys/dev/pci/drm/i915/gt/intel_lrc.c

598

REG(0x038),

sys/dev/pci/drm/i915/gt/intel_lrc.c

599

REG(0x03c),

sys/dev/pci/drm/i915/gt/intel_lrc.c

600

REG(0x168),

sys/dev/pci/drm/i915/gt/intel_lrc.c

601

REG(0x140),

sys/dev/pci/drm/i915/gt/intel_lrc.c

602

REG(0x110),

sys/dev/pci/drm/i915/gt/intel_lrc.c

603

REG(0x1c0),

sys/dev/pci/drm/i915/gt/intel_lrc.c

604

REG(0x1c4),

sys/dev/pci/drm/i915/gt/intel_lrc.c

605

REG(0x1c8),

sys/dev/pci/drm/i915/gt/intel_lrc.c

606

REG(0x180),

sys/dev/pci/drm/i915/gt/intel_lrc.c

608

REG(0x120),

sys/dev/pci/drm/i915/gt/intel_lrc.c

609

REG(0x124),

sys/dev/pci/drm/i915/gt/intel_lrc.c

630

REG(0x0c8),