RD4
static const long double RD4[NRD4 + 1] =
p = z * neval (z, RN4, NRN4) / deval (z, RD4, NRD4);
maclo = RD4(sc, GENET_UMAC_MAC0);
machi = RD4(sc, GENET_UMAC_MAC1);
if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0)
return RD4(sc, GENET_MDIO_CMD) & 0xffff;
if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0)
val = RD4(sc, GENET_EXT_RGMII_OOB_CTRL);
val = RD4(sc, GENET_UMAC_CMD);
cmd = RD4(sc, GENET_UMAC_CMD);
val = RD4(sc, GENET_UMAC_CMD);
val = RD4(sc, GENET_RX_DMA_CTRL);
val = RD4(sc, GENET_TX_DMA_CTRL);
val = RD4(sc, GENET_UMAC_CMD);
val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);
val = RD4(sc, GENET_RBUF_CTRL);
val = RD4(sc, GENET_TX_DMA_CTRL);
val = RD4(sc, GENET_RX_DMA_CTRL);
val = RD4(sc, GENET_UMAC_CMD);
pidx = RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)) & 0xffff;
status = RD4(sc, GENET_RX_DESC_STATUS(index));
queued = (RD4(sc, GENET_TX_DMA_PROD_INDEX(qid)) -
val = RD4(sc, GENET_INTRL2_CPU_STAT);
val &= ~RD4(sc, GENET_INTRL2_CPU_STAT_MASK);