sys/dev/pci/drm/radeon/cik.c

4082

WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);

sys/dev/pci/drm/radeon/cik.c

4083

WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/cik.c

8400

r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

sys/dev/pci/drm/radeon/evergreen.c

3102

((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));

sys/dev/pci/drm/radeon/evergreen.c

3103

WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/evergreen.c

5083

r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

sys/dev/pci/drm/radeon/ni.c

1676

addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;

sys/dev/pci/drm/radeon/ni.c

2228

r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

sys/dev/pci/drm/radeon/r100.c

1167

r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,

sys/dev/pci/drm/radeon/r100.c

1217

S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));

sys/dev/pci/drm/radeon/r600.c

2749

((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));

sys/dev/pci/drm/radeon/r600.c

2750

WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/r600.c

3161

r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

sys/dev/pci/drm/radeon/rv770.c

1814

r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

sys/dev/pci/drm/radeon/si.c

3662

WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);

sys/dev/pci/drm/radeon/si.c

3663

WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/pci/drm/radeon/si.c

6691

r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,