Symbol: RADEON_PPLL_REF_DIV
sys/dev/pci/drm/radeon/radeon_clocks.c
128
p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
sys/dev/pci/drm/radeon/radeon_clocks.c
206
p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
sys/dev/pci/drm/radeon/radeon_clocks.c
284
u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
sys/dev/pci/drm/radeon/radeon_clocks.c
326
RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
sys/dev/pci/drm/radeon/radeon_combios.c
1146
RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
224
RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
232
while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
234
WREG32_PLL_P(RADEON_PPLL_REF_DIV,
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
934
if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
971
WREG32_PLL_P(RADEON_PPLL_REF_DIV,
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
976
WREG32_PLL_P(RADEON_PPLL_REF_DIV,
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
981
WREG32_PLL_P(RADEON_PPLL_REF_DIV,