R92C_AFE_XTAL_CTRL
rtwn_pci_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* differs in btcoex */
rtwn_pci_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
rtwn_pci_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
rtwn_pci_write_4(sc, R92C_AFE_XTAL_CTRL,
(rtwn_pci_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f);
reg = rtwn_pci_read_4(sc, R92C_AFE_XTAL_CTRL);
rtwn_pci_write_4(sc, R92C_AFE_XTAL_CTRL, reg);
reg = rtwn_pci_read_4(sc, R92C_AFE_XTAL_CTRL + 2);
rtwn_pci_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg);
rtwn_pci_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
rtwn_pci_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
rtwn_pci_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb);