sys/dev/pci/drm/radeon/radeon_clocks.c

158

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

sys/dev/pci/drm/radeon/radeon_clocks.c

236

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

sys/dev/pci/drm/radeon/radeon_clocks.c

300

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

sys/dev/pci/drm/radeon/radeon_clocks.c

352

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

sys/dev/pci/drm/radeon/radeon_clocks.c

444

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

sys/dev/pci/drm/radeon/radeon_clocks.c

49

fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);

sys/dev/pci/drm/radeon/radeon_clocks.c

506

tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);

sys/dev/pci/drm/radeon/radeon_clocks.c

509

WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);

sys/dev/pci/drm/radeon/radeon_clocks.c

55

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;

sys/dev/pci/drm/radeon/radeon_clocks.c

79

fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);

sys/dev/pci/drm/radeon/radeon_clocks.c

85

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;