sys/arch/sparc64/dev/ce4231.c

305

CS_WRITE(sc, AD1848_IADDR, r);

sys/arch/sparc64/dev/ce4231.c

315

CS_WRITE(sc, AD1848_IADDR, r);

sys/arch/sparc64/dev/ce4231.c

412

tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)

sys/arch/sparc64/dev/ce4231.c

517

CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE);

sys/arch/sparc64/dev/ce4231.c

518

CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE | SP_INTERFACE_CONFIG);

sys/arch/sparc64/dev/ce4231.c

521

CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE | SP_CLOCK_DATA_FORMAT);

sys/arch/sparc64/dev/ce4231.c

527

tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)

sys/arch/sparc64/dev/ce4231.c

532

CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE | CS_REC_FORMAT);

sys/arch/sparc64/dev/ce4231.c

537

tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)

sys/arch/sparc64/dev/ce4231.c

542

CS_WRITE(sc, AD1848_IADDR, 0);

sys/arch/sparc64/dev/ce4231.c

544

tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)

sys/arch/sparc64/dev/ce4231.c

549

CS_WRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT);

sys/dev/isa/ad1848.c

1142

while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)

sys/dev/isa/ad1848.c

1158

while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)

sys/dev/isa/ad1848.c

1161

if (ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)

sys/dev/isa/ad1848.c

165

ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);

sys/dev/isa/ad1848.c

175

ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);

sys/dev/isa/ad1848.c

188

ADWRITE(sc, AD1848_IADDR, sc->MCE_bit);

sys/dev/isa/ad1848.c

208

while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)

sys/dev/isa/ad1848.c

211

if (ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)

sys/dev/isa/ad1848.c

307

tmp = ADREAD(sc, AD1848_IADDR);

sys/dev/isa/ad1848.c

466

while(ADREAD(sc, AD1848_IADDR) & SP_IN_INIT)

sys/dev/isa/ad1848.c

470

ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT);

sys/dev/isa/ad1848.c

523

while (timeout > 0 && ADREAD(sc, AD1848_IADDR) & SP_IN_INIT)

sys/dev/isa/ad1848.c

541

ADREAD(sc, AD1848_IADDR) & SP_IN_INIT)

sys/dev/sbus/cs4231.c

254

CS_WRITE(sc, AD1848_IADDR, r);

sys/dev/sbus/cs4231.c

264

CS_WRITE(sc, AD1848_IADDR, r);

sys/dev/sbus/cs4231.c

365

tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)

sys/dev/sbus/cs4231.c

547

CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE);

sys/dev/sbus/cs4231.c

548

CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE | SP_INTERFACE_CONFIG);

sys/dev/sbus/cs4231.c

551

CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE | SP_CLOCK_DATA_FORMAT);

sys/dev/sbus/cs4231.c

557

tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)

sys/dev/sbus/cs4231.c

562

CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE | CS_REC_FORMAT);

sys/dev/sbus/cs4231.c

567

tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)

sys/dev/sbus/cs4231.c

572

CS_WRITE(sc, AD1848_IADDR, 0);

sys/dev/sbus/cs4231.c

574

tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)

sys/dev/sbus/cs4231.c

579

CS_WRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT);