sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1108

PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

593

PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

356

HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

558

type PTE_ROW_HEIGHT_LINEAR;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1339

PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1388

PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

217

PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

160

PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

282

PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

457

PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

154

HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

138

HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

239

PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

844

PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

127

HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\