sys/dev/pci/drm/i915/display/intel_display_power.c

1225

intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,

sys/dev/pci/drm/i915/display/intel_lvds.c

332

if (intel_de_wait_for_set(display, PP_STATUS(display, 0), PP_ON, 5000))

sys/dev/pci/drm/i915/display/intel_lvds.c

348

if (intel_de_wait_for_clear(display, PP_STATUS(display, 0), PP_ON, 1000))

sys/dev/pci/drm/i915/display/intel_pps.c

283

return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;

sys/dev/pci/drm/i915/display/intel_pps.c

557

return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;

sys/dev/pci/drm/i915/display/intel_pps.c

595

#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)

sys/dev/pci/drm/i915/display/intel_pps.c

596

#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)

sys/dev/pci/drm/i915/display/intel_pps.c

598

#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)

sys/dev/pci/drm/i915/display/intel_pps.c

601

#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)

sys/dev/pci/drm/i915/gvt/handlers.c

392

vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;

sys/dev/pci/drm/i915/gvt/handlers.c

399

~(PP_ON | PP_SEQUENCE_POWER_DOWN