sys/arch/armv7/marvell/mvpcie.c

660

case PPB_REG_IOSTATUS:

sys/arch/armv7/marvell/mvpcie.c

706

case PPB_REG_IOSTATUS:

sys/dev/fdt/cdpcie.c

177

blr = HREAD4(sc, PPB_REG_IOSTATUS);

sys/dev/fdt/cdpcie.c

356

blr = HREAD4(sc, PPB_REG_IOSTATUS) & 0xffff0000;

sys/dev/fdt/cdpcie.c

359

HWRITE4(sc, PPB_REG_IOSTATUS, blr);

sys/dev/fdt/dwpcie.c

657

HSET4(sc, PPB_REG_IOSTATUS,

sys/dev/fdt/dwpcie.c

690

HWRITE4(sc, PPB_REG_IOSTATUS, blr);

sys/dev/fdt/dwpcie.c

695

HWRITE4(sc, PPB_REG_IOSTATUS, 0x000000ff);

sys/dev/fdt/mvkpcie.c

632

case PPB_REG_IOSTATUS:

sys/dev/pci/pci.c

1019

blr = pci_conf_read(pc, tag, PPB_REG_IOSTATUS);

sys/dev/pci/pci.c

1035

pci_conf_write(pc, tag, PPB_REG_IOSTATUS, blr);

sys/dev/pci/ppb.c

277

blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IOSTATUS);

sys/dev/pci/ppb.c

464

blr = pci_conf_read(pc, tag, PPB_REG_IOSTATUS);

sys/dev/pci/ppb.c

468

pci_conf_write(pc, tag, PPB_REG_IOSTATUS, blr);

sys/dev/pci/ppb.c

669

pci_conf_write(pc, sc->sc_tag, PPB_REG_IOSTATUS, 0x000000ff);

sys/dev/pci/ppb.c

675

blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IOSTATUS);

sys/dev/pci/ppb.c

692

PPB_REG_IOSTATUS);

sys/dev/pci/ppb.c

697

PPB_REG_IOSTATUS, blr);