sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

468

ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

483

ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

497

ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

498

ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

505

ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

507

ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2575

ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2577

ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2584

ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2593

ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2600

ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2602

ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1333

ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1335

ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1342

ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1350

ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1357

ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1359

ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;