sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

2002

ret = amdgpu_dpm_get_dpm_freq_range(adev, PP_SCLK, &min_freq, &max_freq);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

2012

ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

828

if (type != PP_SCLK)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1082

return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1090

return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1038

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

984

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3259

smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4927

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4978

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5631

smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5634

smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1550

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1577

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4280

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4358

vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4698

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4843

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1803

vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2033

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2281

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2574

case PP_SCLK:

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2756

vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3383

case PP_SCLK:

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2655

case PP_SCLK:

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3039

case PP_SCLK: