sys/dev/pci/drm/i915/display/intel_pps.c

595

#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)

sys/dev/pci/drm/i915/display/intel_pps.c

601

#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

36

#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

37

#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

38

#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

39

#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

40

#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

41

#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

42

#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

43

#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)

sys/dev/pci/drm/i915/display/intel_pps_regs.h

44

#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)