sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

383

PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

384

PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

388

PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

399

PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

1087

PP_ASSERT_WITH_CODE((NULL != voltage_info),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

112

PP_ASSERT_WITH_CODE((num_entries <= VBIOS_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

563

PP_ASSERT_WITH_CODE((NULL != voltage_info),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

583

PP_ASSERT_WITH_CODE((NULL != voltage_info),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

592

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

660

PP_ASSERT_WITH_CODE((NULL != table_address),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

678

PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

87

PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

106

PP_ASSERT_WITH_CODE(voltage_info,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

118

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

154

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

64

PP_ASSERT_WITH_CODE(table_address,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

85

PP_ASSERT_WITH_CODE(voltage_info,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1126

PP_ASSERT_WITH_CODE((ATOM_Tonga_TABLE_REVISION_TONGA <=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1129

PP_ASSERT_WITH_CODE((0 != powerplay_table->usStateArrayOffset),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1131

PP_ASSERT_WITH_CODE((0 < powerplay_table->sHeader.usStructureSize),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1133

PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1146

PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1151

PP_ASSERT_WITH_CODE((NULL != powerplay_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1156

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1162

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1167

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1172

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1177

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1182

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1245

PP_ASSERT_WITH_CODE((NULL != pp_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1247

PP_ASSERT_WITH_CODE((pp_table->sHeader.ucTableFormatRevision >=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1321

PP_ASSERT_WITH_CODE((i < vce_state_table->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1378

PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1386

PP_ASSERT_WITH_CODE((0 < pp_table->usStateArrayOffset),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1388

PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1390

PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

165

PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

321

PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

348

PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

371

PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

415

PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

444

PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

491

PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

528

PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

57

PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

59

PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

61

PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

63

PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

65

PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

725

PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

771

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

919

PP_ASSERT_WITH_CODE((0 != powerplay_table->usThermalControllerOffset),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

953

PP_ASSERT_WITH_CODE((0 != powerplay_table->usFanTableOffset),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

955

PP_ASSERT_WITH_CODE((0 < fan_table->ucRevId),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1186

PP_ASSERT_WITH_CODE(fw_info != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1711

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1717

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1722

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1727

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1733

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1738

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1743

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

852

PP_ASSERT_WITH_CODE(NULL != powerplay_tab,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

198

PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

504

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1132

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1139

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1155

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1207

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1218

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1295

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1302

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1312

PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1328

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1336

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1358

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1368

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1571

PP_ASSERT_WITH_CODE(tmp_result == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1576

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1593

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1598

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1602

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1606

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1611

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1617

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1621

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1625

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1631

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1640

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1645

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1649

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1653

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1657

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1661

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1665

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1669

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1673

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1677

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1681

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1685

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1701

PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1708

PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1746

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1750

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1754

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1763

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1767

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1771

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1775

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1779

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1783

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1787

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1791

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1795

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

180

PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

190

PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2085

PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2250

PP_ASSERT_WITH_CODE((NULL != look_up_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2252

PP_ASSERT_WITH_CODE((0 != look_up_table->count),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2256

PP_ASSERT_WITH_CODE((i >= look_up_table->count),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

231

PP_ASSERT_WITH_CODE((7 >= link_width),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2355

PP_ASSERT_WITH_CODE(0 != lookup_table->count,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2456

PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2459

PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2463

PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2466

PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2849

PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2852

PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2856

PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2859

PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

293

PP_ASSERT_WITH_CODE((NULL != voltage_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

328

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

339

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

348

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

358

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3644

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3649

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

367

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

376

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3808

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3813

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

387

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

392

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

399

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

406

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

413

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4221

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4224

PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4235

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4238

PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4279

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4288

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4323

PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4378

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4381

PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4392

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4395

PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4486

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4494

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4500

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4504

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4516

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4521

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4526

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4531

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4536

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4541

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4549

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4892

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4896

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4900

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4904

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4908

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4912

PP_ASSERT_WITH_CODE((0 == tmp_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5361

PP_ASSERT_WITH_CODE(valid_entry,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5504

PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5515

PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5522

PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5735

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5813

PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

645

PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

792

PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

794

PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

797

PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

799

PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

816

PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

883

PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

886

PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

890

PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

893

PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1000

PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1002

PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1005

PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1007

PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1013

PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", goto error);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1019

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1027

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1035

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1041

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1071

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1078

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1100

PP_ASSERT_WITH_CODE((0 == smc_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1117

PP_ASSERT_WITH_CODE((smc_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1167

PP_ASSERT_WITH_CODE((0 == smc_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1178

PP_ASSERT_WITH_CODE((0 == smc_result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1208

PP_ASSERT_WITH_CODE((smc_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1218

PP_ASSERT_WITH_CODE((smc_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1228

PP_ASSERT_WITH_CODE((smc_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

904

PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

985

PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

987

PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

990

PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

997

PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

459

PP_ASSERT_WITH_CODE((0 == ret && NULL != table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

465

PP_ASSERT_WITH_CODE((vddc_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

467

PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

469

PP_ASSERT_WITH_CODE((acp_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

471

PP_ASSERT_WITH_CODE((uvd_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

473

PP_ASSERT_WITH_CODE((vce_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

211

PP_ASSERT_WITH_CODE((NULL != vol_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

254

PP_ASSERT_WITH_CODE((0 != dep_table->count),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

257

PP_ASSERT_WITH_CODE((NULL != vol_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

270

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

282

PP_ASSERT_WITH_CODE((0 != dep_table->count),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

285

PP_ASSERT_WITH_CODE((NULL != vol_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

298

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

309

PP_ASSERT_WITH_CODE((0 != lookup_table->count),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

312

PP_ASSERT_WITH_CODE((NULL != vol_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

395

PP_ASSERT_WITH_CODE((NULL != lookup_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

397

PP_ASSERT_WITH_CODE((0 != count),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

415

PP_ASSERT_WITH_CODE((NULL != voltage_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

417

PP_ASSERT_WITH_CODE((0 != count),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

469

PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

694

PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1003

PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1030

PP_ASSERT_WITH_CODE(vol_table,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1072

PP_ASSERT_WITH_CODE(dep_table->count,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

108

PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1085

PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1099

PP_ASSERT_WITH_CODE(dep_table->count,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1112

PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1125

PP_ASSERT_WITH_CODE(dep_table->count,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1182

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1191

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1201

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1206

PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1211

PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1216

PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1268

PP_ASSERT_WITH_CODE(bios_pcie_table->count,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1332

PP_ASSERT_WITH_CODE(dep_soc_table,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1335

PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1339

PP_ASSERT_WITH_CODE(dep_gfx_table,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1342

PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1346

PP_ASSERT_WITH_CODE(dep_mclk_table,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1349

PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1505

PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1632

PP_ASSERT_WITH_CODE(dep_on_sclk,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1643

PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1648

PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1706

PP_ASSERT_WITH_CODE(dep_on_soc->count > i,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1710

PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1836

PP_ASSERT_WITH_CODE(dep_on_mclk,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1847

PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1852

PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1864

PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1950

PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1981

PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2000

PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2052

PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2068

PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2454

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2461

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2520

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2575

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2594

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2621

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2627

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2632

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2637

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2642

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2649

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2654

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2659

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2665

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2701

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2706

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2723

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2727

PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2742

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2762

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2780

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2789

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2807

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2822

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2837

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2845

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2853

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2861

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2876

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2884

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2892

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2900

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2919

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2974

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2989

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2998

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3016

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3063

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3070

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3078

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3084

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3089

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3096

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3108

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3114

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3119

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3192

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3198

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3334

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3508

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3516

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3567

PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3760

PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3777

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3780

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3801

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3843

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3848

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3853

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3858

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3863

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4162

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4166

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4184

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4188

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4209

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4213

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4284

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4288

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4297

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4301

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4311

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4315

PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4608

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4977

PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4995

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5103

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5107

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5111

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5115

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5119

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5123

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5127

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5140

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

533

PP_ASSERT_WITH_CODE(lookup_table->count != 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

544

PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5604

PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5674

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5734

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

588

PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

595

PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

725

PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

784

PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

786

PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

789

PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

791

PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

865

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

900

PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

946

PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

98

PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

999

PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1138

PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1155

PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1159

PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1163

PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1169

PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1173

PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1182

PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1202

PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1206

PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1210

PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1216

PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1220

PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1229

PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1304

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1310

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1316

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1330

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1336

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

753

PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1041

PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1154

PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1159

PP_ASSERT_WITH_CODE((powerplay_table != NULL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1164

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1170

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1175

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1180

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1185

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1190

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1253

PP_ASSERT_WITH_CODE((pp_table != NULL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1255

PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1305

PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1315

PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1318

PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

132

PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1321

PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1349

PP_ASSERT_WITH_CODE((powerplay_table != NULL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1354

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

170

PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

350

PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

573

PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

603

PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

640

PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

682

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

702

PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

738

PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

75

PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

78

PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

793

PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

80

PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

82

PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

831

PP_ASSERT_WITH_CODE(limit_table->ucNumEntries,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

853

PP_ASSERT_WITH_CODE(clk_volt_pp_table->count,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

185

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

202

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

219

PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

235

PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

442

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

473

PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1000

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1007

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1014

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1030

PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1065

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1070

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1075

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1080

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1085

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1090

PP_ASSERT_WITH_CODE(!tmp_result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1095

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1100

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1105

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1142

PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1167

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1177

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1185

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1196

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1205

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1216

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1227

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1238

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1259

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1270

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1281

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1289

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1300

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1311

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1328

PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1349

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1354

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1372

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1377

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1433

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1450

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1639

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1673

PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1677

PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1702

PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1706

PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1716

PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1720

PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2043

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2048

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2063

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2068

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2091

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2096

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2116

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2178

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2282

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2287

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2298

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2303

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2314

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2321

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2332

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2339

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2525

PP_ASSERT_WITH_CODE(dpm_table->count > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2528

PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2533

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2569

PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2589

PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2644

PP_ASSERT_WITH_CODE((tmp_result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2656

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2858

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

472

PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

542

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

559

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

569

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

587

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

601

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

617

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

625

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

657

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

670

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

683

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

696

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

709

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

722

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

735

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

748

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

759

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

770

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

853

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

863

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

868

PP_ASSERT_WITH_CODE(result == 1,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

887

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

893

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

925

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

951

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

105

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

267

PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

271

PP_ASSERT_WITH_CODE((powerplay_table != NULL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

275

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

280

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

284

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

362

PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

372

PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

375

PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

378

PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

67

PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

70

PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

109

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

123

PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

34

PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

74

PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

92

PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1035

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1238

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1265

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1294

PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1302

PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1310

PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1393

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1412

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1469

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1509

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1515

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1555

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1561

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1592

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1601

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1628

PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1635

PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1642

PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1647

PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1652

PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1657

PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1677

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1701

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1706

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1711

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1716

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1721

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1726

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1731

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1736

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1744

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1749

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1754

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1759

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1767

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1798

PP_ASSERT_WITH_CODE(table != NULL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1801

PP_ASSERT_WITH_CODE(table->count > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1804

PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1830

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1841

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1853

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1862

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1874

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1886

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1898

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1910

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1932

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1944

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1956

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1964

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1976

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1988

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2000

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2028

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2046

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2052

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2070

PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2076

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2081

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2096

PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2102

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2107

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2176

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2367

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2380

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2419

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2426

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2461

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2468

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2519

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2526

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2591

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2596

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2618

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2623

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2646

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2651

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2674

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2679

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2699

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2717

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2981

PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3141

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3150

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3201

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3257

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3385

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3403

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3421

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3439

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3451

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3591

PP_ASSERT_WITH_CODE(dpm_table->count > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3594

PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3599

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3617

PP_ASSERT_WITH_CODE(dpm_table->count > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3620

PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3625

PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3662

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3697

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3939

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3952

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4024

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4115

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4179

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4273

PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

508

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

545

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

561

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

575

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

583

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

603

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

624

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

656

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

683

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

696

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

709

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

722

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

735

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

746

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

757

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

768

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

801

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

827

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

888

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

905

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

915

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

945

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

951

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

977

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

984

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

147

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

340

PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

344

PP_ASSERT_WITH_CODE((powerplay_table != NULL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

348

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

353

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

357

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

69

PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

72

PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

108

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

42

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

71

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1047

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1190

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1199

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1208

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1317

PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1367

PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1407

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1540

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1547

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1579

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1610

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1636

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1732

PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1843

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1847

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1971

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1979

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1983

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1987

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1991

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1995

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1999

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2005

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2009

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2021

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2025

PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2028

PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2054

PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2062

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2109

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2113

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2117

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2239

PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2242

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2559

PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2561

PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2591

PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2607

PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2623

PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

315

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

552

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

585

PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

587

PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

589

PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

613

PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

773

PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

853

PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

883

PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

911

PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

933

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

937

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

941

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

958

PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1047

PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1149

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1180

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1235

PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1287

PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1321

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1335

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1379

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1445

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1482

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

149

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1505

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1580

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1587

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1732

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1831

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1949

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1956

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1960

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1964

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1968

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1972

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1976

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1984

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1988

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1992

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1996

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2000

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2006

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2032

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2110

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2114

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2118

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2122

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2287

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

229

PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

244

PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

252

PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

265

PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

269

PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

273

PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

507

PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

613

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

700

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

706

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

711

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

715

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

722

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

728

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

734

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

740

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

747

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

788

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

873

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

958

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1069

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1243

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1254

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1362

PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1412

PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1453

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1597

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

164

PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1697

PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

178

PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1809

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1813

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1923

PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1959

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1967

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1971

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1975

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1979

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1983

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1987

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1993

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1997

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2004

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2008

PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2011

PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2035

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2063

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2075

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2079

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2202

PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2205

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2486

PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2488

PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2518

PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2534

PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2551

PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

345

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

396

PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

398

PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

400

PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

409

PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

422

PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

446

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

452

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

458

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

464

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

469

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

473

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

480

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

486

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

492

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

499

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

540

PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

629

PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

656

PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

681

PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

700

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

704

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

708

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

725

PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

813

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

904

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1086

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1107

PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1173

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1224

PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1268

PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1297

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1303

PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

131

PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1332

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1403

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

142

PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1452

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1475

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

149

PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1557

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1564

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

157

PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

166

PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1699

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1729

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

182

PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

188

PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

193

PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1946

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1953

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1957

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1961

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1965

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1969

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1973

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1981

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1985

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1989

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1993

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1997

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2005

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2011

PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2035

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2095

PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2124

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2128

PP_ASSERT_WITH_CODE(0 == result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

239

PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2407

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2411

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

309

PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

445

PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

531

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

615

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

620

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

625

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

629

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

635

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

640

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

645

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

650

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

657

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

979

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

123

PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

125

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

127

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

157

PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

159

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

161

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

343

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

346

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

349

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

352

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

355

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

358

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

361

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

364

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

367

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

371

PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

40

PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

41

PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

422

PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

432

PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

58

PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

59

PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1108

PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1162

PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1201

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1344

PP_ASSERT_WITH_CODE((!result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1352

PP_ASSERT_WITH_CODE((!result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1401

PP_ASSERT_WITH_CODE((!result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1446

PP_ASSERT_WITH_CODE((!result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1472

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1661

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1843

PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1920

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2006

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2012

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2017

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2022

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2028

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2034

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2041

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2047

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2056

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2072

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2191

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2196

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2260

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2269

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2273

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2277

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2281

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2285

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2289

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2297

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2302

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2306

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2310

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2316

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2346

PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2355

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2442

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2446

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2450

PP_ASSERT_WITH_CODE((!result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2454

PP_ASSERT_WITH_CODE((!result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2592

PP_ASSERT_WITH_CODE((!result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2597

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2950

PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2952

PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2982

PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2999

PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3015

PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

452

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

457

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

462

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

467

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

472

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

556

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

638

PP_ASSERT_WITH_CODE((!result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

736

PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

812

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

987

PP_ASSERT_WITH_CODE(

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

185

PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

364

PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

44

PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

46

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

48

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

83

PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

85

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

87

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

103

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

109

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

115

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

134

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

138

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

143

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

147

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

164

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

170

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

378

PP_ASSERT_WITH_CODE(smu9_is_smc_ram_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

47

PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

49

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

51

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

53

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

58

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

64

PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

91

PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

93

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

95

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

171

PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

173

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

175

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

178

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

184

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

190

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

216

PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

218

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

220

PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

228

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

234

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

240

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

261

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

267

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

273

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

291

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

297

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

303

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

327

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

331

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

336

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

340

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

358

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

363

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

402

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

408

PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

594

PP_ASSERT_WITH_CODE(ret,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

599

PP_ASSERT_WITH_CODE(!ret,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1001

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1050

PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1101

PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1130

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1137

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1168

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1232

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1258

PP_ASSERT_WITH_CODE(result == 0,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1344

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1351

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

139

PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1456

PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1535

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1683

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1709

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1771

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1855

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1860

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1865

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1869

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1875

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1880

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1885

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1890

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1898

PP_ASSERT_WITH_CODE(false,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1954

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1961

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1965

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1969

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1973

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1977

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1985

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1989

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1993

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1997

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2001

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2007

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2013

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2034

PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2043

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2106

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

211

PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2139

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2143

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2147

PP_ASSERT_WITH_CODE(!result,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2237

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2241

PP_ASSERT_WITH_CODE((result == 0),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2269

PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

797

PP_ASSERT_WITH_CODE((clock >= min),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

827

PP_ASSERT_WITH_CODE((0 == result),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

918

PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

968

PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

995

PP_ASSERT_WITH_CODE(!result,