sys/dev/pci/drm/i915/display/intel_bios.c

2350

[PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT },

sys/dev/pci/drm/i915/display/intel_bios.c

2964

else if (port == PORT_E)

sys/dev/pci/drm/i915/display/intel_bios.c

2969

if (port != PORT_A && port != PORT_E)

sys/dev/pci/drm/i915/display/intel_bios.c

2972

if (port != PORT_E)

sys/dev/pci/drm/i915/display/intel_crt.c

1087

assert_port_valid(display, PORT_E);

sys/dev/pci/drm/i915/display/intel_crt.c

1089

crt->base.port = PORT_E;

sys/dev/pci/drm/i915/display/intel_ddi.c

1122

_skl_ddi_set_iboost(display, PORT_E, iboost);

sys/dev/pci/drm/i915/display/intel_ddi.c

2896

is_mst && (port == PORT_A || port == PORT_E));

sys/dev/pci/drm/i915/display/intel_ddi.c

3394

[PORT_E] = TRANSCODER_A,

sys/dev/pci/drm/i915/display/intel_ddi.c

3399

if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E))

sys/dev/pci/drm/i915/display/intel_ddi.c

3444

if (port == PORT_E)

sys/dev/pci/drm/i915/display/intel_ddi.c

3456

if (port == PORT_E)

sys/dev/pci/drm/i915/display/intel_ddi.c

4890

if (port == PORT_A || port == PORT_E) {

sys/dev/pci/drm/i915/display/intel_ddi.c

5039

case PORT_E:

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c

1178

if (port == PORT_A || port == PORT_E)

sys/dev/pci/drm/i915/display/intel_display.h

109

case PORT_E:

sys/dev/pci/drm/i915/display/intel_display_device.c

586

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),

sys/dev/pci/drm/i915/display/intel_display_device.c

639

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),

sys/dev/pci/drm/i915/display/intel_display_device.c

683

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),

sys/dev/pci/drm/i915/display/intel_display_device.c

932

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),

sys/dev/pci/drm/i915/display/intel_dp_aux.c

846

if (DISPLAY_VER(display) == 9 && encoder->port == PORT_E)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1875

if (DISPLAY_VER(display) < 11 && port == PORT_E)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3371

if (port == PORT_D || port == PORT_E) {

sys/dev/pci/drm/i915/display/intel_fdi.c

893

intel_de_write(display, DP_TP_CTL(PORT_E),

sys/dev/pci/drm/i915/display/intel_fdi.c

903

intel_de_write(display, DDI_BUF_CTL(PORT_E),

sys/dev/pci/drm/i915/display/intel_fdi.c

907

intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

930

temp = intel_de_read(display, DP_TP_STATUS(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

950

intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

951

intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

954

intel_de_rmw(display, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

955

intel_de_posting_read(display, DP_TP_CTL(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

957

intel_wait_ddi_buf_idle(display, PORT_E);

sys/dev/pci/drm/i915/display/intel_fdi.c

967

intel_de_write(display, DP_TP_CTL(PORT_E),

sys/dev/pci/drm/i915/display/intel_fdi.c

985

intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

986

intel_wait_ddi_buf_idle(display, PORT_E);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1218

(DISPLAY_VER(display) >= 12 || port < PORT_E);

sys/dev/pci/drm/i915/display/intel_hdcp.c

472

case PORT_E:

sys/dev/pci/drm/i915/display/intel_opregion.c

414

if (port == PORT_E) {

sys/dev/pci/drm/i915/gvt/display.c

498

intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {

sys/dev/pci/drm/i915/gvt/edid.c

122

port = PORT_E;

sys/dev/pci/drm/i915/gvt/edid.c

98

port = PORT_E;

sys/dev/pci/drm/i915/gvt/handlers.c

2374

MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2380

MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2386

MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);

sys/dev/pci/drm/i915/gvt/handlers.c

817

if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))

sys/dev/pci/drm/i915/gvt/handlers.c

818

vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))

sys/dev/pci/drm/i915/gvt/handlers.c

836

u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/gvt/handlers.c

838

u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));

sys/dev/pci/drm/i915/gvt/handlers.c

952

vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=

sys/dev/pci/drm/i915/gvt/handlers.c

958

calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

502

MMIO_D(PORT_CLK_SEL(PORT_E));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

533

MMIO_D(DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

538

MMIO_D(DP_TP_CTL(PORT_E));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

543

MMIO_D(DP_TP_STATUS(PORT_E));