PORT_A
if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A)
if (display->platform.ivybridge && port == PORT_A) {
if ((display->platform.ivybridge && port == PORT_A) ||
(HAS_PCH_CPT(display) && port != PORT_A)) {
else if (display->platform.ivybridge && port == PORT_A)
else if (display->platform.sandybridge && port == PORT_A)
(HAS_PCH_SPLIT(display) && port != PORT_A)) {
if (port == PORT_A)
if (port != PORT_A)
} else if (HAS_PCH_CPT(display) && port != PORT_A) {
if (display->platform.ivybridge && port == PORT_A)
else if (HAS_PCH_CPT(display) && port != PORT_A)
pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
if (HAS_PCH_CPT(display) && port != PORT_A) {
if (port == PORT_A) {
if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) {
if (port == PORT_A)
if (port == PORT_A)
if (port == PORT_A)
port == PORT_A ?
if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
port = PORT_A;
port == PORT_A ?
if (drm_WARN_ON(display->drm, port == PORT_A))
if (drm_WARN_ON(display->drm, port == PORT_A))
panel->vbt.dsi.bl_ports = BIT(PORT_A);
panel->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(port_bc);
panel->vbt.dsi.cabc_ports = BIT(PORT_A);
BIT(PORT_A) | BIT(port_bc);
for (port = PORT_A; port < n_ports; port++) {
[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
return PORT_A;
if (port != PORT_A || DISPLAY_VER(display) >= 12)
if (port != PORT_A && port != PORT_E)
if (port == PORT_A)
bool ddi_a_present = intel_bios_is_port_present(display, PORT_A);
if ((display->platform.battlemage && encoder->port == PORT_A) ||
(port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
if (encoder->port == PORT_A && dig_port->max_lanes == 4)
case PORT_A:
is_mst && (port == PORT_A || port == PORT_E));
drm_WARN_ON(display->drm, is_mst && port == PORT_A);
if ((port != PORT_A || DISPLAY_VER(display) >= 9) &&
if (port == PORT_A && DISPLAY_VER(display) < 9)
[PORT_A] = TRANSCODER_EDP,
if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E))
port = PORT_A;
if (port == PORT_A && DISPLAY_VER(display) < 12)
if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
if (dig_port->base.port != PORT_A)
if (port == PORT_A || port == PORT_E) {
if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
max_lanes = port == PORT_A ? 4 : 0;
return HPD_PORT_A + port - PORT_A;
return HPD_PORT_A + port - PORT_A;
return HPD_PORT_A + port - PORT_A;
return HPD_PORT_A + port - PORT_A;
return HPD_PORT_A + port - PORT_A;
return HPD_PORT_A + port - PORT_A;
return HPD_PORT_A + port - PORT_A;
case PORT_A:
return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
if (port == PORT_A)
if (port == PORT_A)
if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) {
if (port == PORT_A || port == PORT_E)
return PHY_A + port - PORT_A;
for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
if (port == PORT_A)
if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
g4x_dp_init(display, DP_A, PORT_A);
case PORT_A:
for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
lpsp_capable = (encoder->port == PORT_A &&
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
.__runtime_defaults.port_mask = BIT(PORT_A) |
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2),
.__runtime_defaults.port_mask = BIT(PORT_A) |
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
PORT_A : PORT_B;
dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
port = PORT_A;
.port_start = PORT_A,
.port_start = PORT_A,
.port_start = PORT_A,
.port_start = PORT_A,
if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&
if (DISPLAY_VER(display) < 12 && port == PORT_A)
encoder->port != PORT_A);
if (DISPLAY_VER(display) < 9 && port == PORT_A)
if (port == PORT_A)
if (!display->platform.g4x && port != PORT_A)
if (DISPLAY_VER(display) < 12 && port == PORT_A)
[DPIO_CH0] = { .port = PORT_A },
[DPIO_CH0] = { .port = PORT_A },
port != PORT_A) {
return PORT_A;
.port = PORT_A,
case PORT_A:
case PORT_A:
drm_WARN_ON(display->drm, encoder->port == PORT_A);
if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A))
return HPD_PORT_A + port - PORT_A;
if (encoder->port == PORT_A)
case PORT_A:
g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe);
return pipe == PIPE_A && port == PORT_A;
if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) {
tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));
intel_de_write(display, MIPI_CTRL(display, PORT_A),
MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A),
else if (port == PORT_A)
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A);
if ((display->platform.broxton || port == PORT_A) &&
if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
*pipe = port == PORT_A ? PIPE_A : PIPE_B;
if (intel_dsi->ports & (1 << PORT_A))
#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
for (port = PORT_A; port <= PORT_C; port++) {
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
(((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
case PORT_A:
calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
MMIO_D(BXT_PHY_CTL(PORT_A));
MMIO_D(BXT_PORT_PLL_ENABLE(PORT_A));
MMIO_D(PORT_CLK_SEL(PORT_A));
MMIO_D(DDI_BUF_CTL(PORT_A));
MMIO_D(DP_TP_CTL(PORT_A));
MMIO_D(DP_TP_STATUS(PORT_A));