sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

267

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

270

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

284

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

365

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

368

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

371

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

384

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

395

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

403

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

416

dcn3_init_single_clock(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

421

clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1003

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1006

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1009

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1022

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1036

dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1039

clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1113

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1123

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

718

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

719

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

721

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

724

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

757

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

760

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

245

if (clk == PPCLK_UCLK)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1009

block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1019

dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1067

if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

125

case PPCLK_UCLK:

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1335

if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1385

dcn401_init_single_clock(clk_mgr, PPCLK_UCLK,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1393

clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

781

bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

783

dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

84

case PPCLK_UCLK:

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

892

if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

908

if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

916

if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

352

success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

374

success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1179

(PPCLK_UCLK << 16) | (min_freq & 0xffff),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1187

(PPCLK_UCLK << 16) | (min_freq & 0xffff),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1272

(PPCLK_UCLK << 16) | (max_freq & 0xffff),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1373

vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1378

vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1451

smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2535

(PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2909

gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

682

ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1630

PPCLK_UCLK)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1843

(PPCLK_UCLK << 16) | (min_freq & 0xffff),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1946

(PPCLK_UCLK << 16) | (max_freq & 0xffff),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2101

ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2106

ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2233

PPCLK_UCLK,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2382

(PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3402

ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3601

(PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4358

gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

623

ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

169

CLK_MAP(UCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

170

CLK_MAP(MCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1915

gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

413

!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

659

*value = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

764

case PPCLK_UCLK:

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

976

(PPCLK_UCLK << 16) | (freq & 0xffff),

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1018

!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1200

case PPCLK_UCLK:

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

154

CLK_MAP(UCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

155

CLK_MAP(MCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2315

num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2995

gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3209

gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3282

gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3361

gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

578

*value = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

664

*value = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

753

*value = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

839

*value = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1008

!table_member[PPCLK_UCLK].SnapToDiscrete;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1212

case PPCLK_UCLK:

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

169

CLK_MAP(UCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

170

CLK_MAP(MCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2062

num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2791

gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2792

use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

789

*value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

790

use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

791

metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1013

(PPCLK_UCLK << 16) | (freq & 0xffff),

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

162

CLK_MAP(UCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

163

CLK_MAP(MCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1810

gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

687

*value = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

790

case PPCLK_UCLK:

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1025

case PPCLK_UCLK:

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

182

CLK_MAP(UCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

183

CLK_MAP(MCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2161

gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

763

*value = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1612

(PPCLK_UCLK << 16) | (freq & 0xffff), NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

187

CLK_MAP(UCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

188

CLK_MAP(MCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1014

case PPCLK_UCLK:

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

153

CLK_MAP(UCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

154

CLK_MAP(MCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2142

gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

755

*value = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

146

CLK_MAP(UCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

147

CLK_MAP(MCLK, PPCLK_UCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2246

gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

687

*value = metrics->CurrClock[PPCLK_UCLK];

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

942

case PPCLK_UCLK: