PPCLK_FCLK
dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
case PPCLK_FCLK:
dcn401_init_single_clock(clk_mgr, PPCLK_FCLK,
clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK) &&
dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_FCLK);
if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
case PPCLK_FCLK:
(PPCLK_FCLK << 16) | (min_freq & 0xffff),
(PPCLK_FCLK << 16) | (max_freq & 0xffff),
ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
(PPCLK_FCLK << 16) | dpm_table->dpm_state.soft_min_level,
ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
CLK_MAP(FCLK, PPCLK_FCLK),
!driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
*value = metrics->CurrClock[PPCLK_FCLK];
case PPCLK_FCLK:
!table_member[PPCLK_FCLK].SnapToDiscrete;
case PPCLK_FCLK:
CLK_MAP(FCLK, PPCLK_FCLK),
*value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
metrics->CurrClock[PPCLK_FCLK];
CLK_MAP(FCLK, PPCLK_FCLK),
*value = metrics->CurrClock[PPCLK_FCLK];
case PPCLK_FCLK:
case PPCLK_FCLK:
CLK_MAP(FCLK, PPCLK_FCLK),
*value = metrics->CurrClock[PPCLK_FCLK];
CLK_MAP(FCLK, PPCLK_FCLK),
case PPCLK_FCLK:
CLK_MAP(FCLK, PPCLK_FCLK),
*value = metrics->CurrClock[PPCLK_FCLK];
CLK_MAP(FCLK, PPCLK_FCLK),
*value = metrics->CurrClock[PPCLK_FCLK];
case PPCLK_FCLK: