PORT_WR_8
PORT_WR_8(sc, BGX_GMP_GMI_TX_APPEND, val);
PORT_WR_8(sc, BGX_GMP_GMI_TX_MIN_PKT, 59);
PORT_WR_8(sc, BGX_GMP_GMI_TX_THRESH, 0x20);
PORT_WR_8(sc, BGX_GMP_GMI_TX_SGMII_CTL, val);
PORT_WR_8(sc, BGX_GMP_PCS_LINK_TIMER, val);
PORT_WR_8(sc, BGX_GMP_PCS_MR_CONTROL, val);
PORT_WR_8(sc, BGX_GMP_PCS_MISC_CTL, misc_ctl);
PORT_WR_8(sc, BGX_CMR_CONFIG, val);
PORT_WR_8(sc, BGX_GMP_PCS_MR_CONTROL_RESET, val);
PORT_WR_8(sc, BGX_GMP_PCS_MISC_CTL, val);
PORT_WR_8(sc, BGX_GMP_PCS_MR_CONTROL, val);
PORT_WR_8(sc, BGX_CMR_CONFIG, config);
PORT_WR_8(sc, BGX_GMP_GMI_TX_SLOT, tx_slot);
PORT_WR_8(sc, BGX_GMP_GMI_TX_BURST, tx_burst);
PORT_WR_8(sc, BGX_GMP_PCS_MISC_CTL, misc_ctl);
PORT_WR_8(sc, BGX_GMP_GMI_PRT_CFG, prt_cfg);
PORT_WR_8(sc, BGX_CMR_CONFIG, config);
PORT_WR_8(sc, c->c_reg, 0);
PORT_WR_8(sc, BGX_CMR_RX_ID_MAP, val);
PORT_WR_8(sc, BGX_CMR_CHAN_MSK_AND, val);
PORT_WR_8(sc, BGX_CMR_CHAN_MSK_OR, val);
PORT_WR_8(sc, BGX_CMR_CONFIG, val);
PORT_WR_8(sc, BGX_CMR_RX_ADR_CTL, rx_adr_ctl);