sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

154

*tmds_div = val_tmds_div == 0 ? PIXEL_RATE_DIV_BY_2 : PIXEL_RATE_DIV_BY_4;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

169

if (tmds_div != PIXEL_RATE_DIV_BY_2 && tmds_div != PIXEL_RATE_DIV_BY_4) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

342

*k2_div = PIXEL_RATE_DIV_BY_2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

348

*k2_div = PIXEL_RATE_DIV_BY_2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

353

*k2_div = PIXEL_RATE_DIV_BY_2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1199

*k2_div = PIXEL_RATE_DIV_BY_2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1205

*k2_div = PIXEL_RATE_DIV_BY_2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1211

*k2_div = PIXEL_RATE_DIV_BY_2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

710

*tmds_div = PIXEL_RATE_DIV_BY_2;