sys/dev/pci/drm/i915/display/intel_display.c

2604

PIPE_DATA_M1(display, transcoder),

sys/dev/pci/drm/i915/display/intel_display.c

3334

PIPE_DATA_M1(display, transcoder),

sys/dev/pci/drm/i915/display/intel_fdi.c

491

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

592

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

729

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/gvt/display.c

272

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

sys/dev/pci/drm/i915/gvt/display.c

273

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

sys/dev/pci/drm/i915/gvt/display.c

409

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

sys/dev/pci/drm/i915/gvt/display.c

410

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

277

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

285

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

293

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

301

MMIO_D(PIPE_DATA_M1(display, TRANSCODER_EDP));